Field programmable gate array

Patent metadata

Field	Value
Publication number	US-10216566-B2
Application number	US-201515737549-A
Country	US
Kind code	B2
Filing date	Jun 22, 2015
Priority date	Jun 22, 2015
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

An object of the invention is to provide a field programmable gate array which is able to prevent an inappropriate value from being output to the outside of an FPGA even when an SRAM-based programmable logic portion is out of order and to secure safety of a system. The field programmable gate array of the invention includes a hard macro CPU in which a circuit structure is fixed, a programmable logic in which a circuit structure is changeable, a diagnosis circuit which diagnoses an abnormality of the programmable logic, and a fail-safe interface circuit which is able to control an external output from the programmable logic to a safe side, and the hard macro CPU outputs a fail-safe signal which is an output of a safe side to the fail-sate interface circuit when an error is detected by the diagnosis circuit.

First claim

The invention claimed is:

1. A field programmable gate array, comprising:
a hard macro CPU in which a circuit structure is fixed;
a programmable logic in which a circuit structure is changeable;
a diagnosis circuit which diagnoses an abnormality of the programmable logic;
a fail-safe interface circuit which is able to control an external output from the programmable logic to a safe side; and
a function in which the hard macro CPU is instructed to output a fail-safe signal which is an output to a safe side to the fail-safe interface circuit when an error is detected by the diagnosis circuit;
wherein the fail-safe interface circuit is provided in the programmable logic, and
wherein an instruction from the hard macro CPU to the fail-safe interface circuit is issued through a communication path in which data is able to be transmitted only from the hard macro to the programmable logic.

2. The field programmable gate array according to claim 1 ,
wherein the fail-safe interface circuit is mounted in the hard macro.

3. The field programmable gate array according to claim 1 ,
wherein the fail-safe interface is controlled by a software program which is executed by the hard macro CPU.

4. The field programmable gate array according to claim 1 ,
wherein the diagnosis circuit diagnoses the programmable logic using a cyclic redundancy check or an error correcting code of a configuration random access memory.

5. The field programmable gate array according to claim 1 ,
wherein the fail-safe signal is output from the fail-safe interface circuit to the control system when a starting-up process of a control system connected to the field programmable gate array starts, and
wherein an output of the fail-safe signal from the fail-safe interface circuit to the control system is ended when the starting-up process of the control system is ended.

6. The field programmable gate array according to claim 1 ,
wherein a high potential (High) fixed value or a low potential (Low) fixed value is output as the fail-safe signal from the fail-safe interface.

7. The field programmable gate array according to claim 1 ,
wherein an alternate signal in which a high potential (High) and a low potential (Low) are repeated at a certain interval is output as the fail-safe signal from the fail-safe interface.

8. The field programmable gate array according to claim 1 ,
wherein a command configured by a plurality of bits is output as the fail-safe signal from the fail-safe interface.

9. The field programmable gate array according to claim 1 ,
wherein external terminals of the field programmable gate array is divided into
an external terminal which is connected dedicatedly to the hard macro CPU,
an external terminal which is connected dedicatedly to the programmable logic, and
an external terminal which is connected dedicatedly to the fail-safe interface circuit.

10. The field programmable gate array according to claim 9 ,
wherein the field programmable gate array includes the external terminals along four sides of a package.

11. The field programmable gate array according to claim 9 ,
wherein the field programmable gate array includes the external terminals in a bottom surface of a package.

12. A field programmable gate array, comprising:
a hard macro CPU in which a circuit structure is fixed;
a programmable logic in which a circuit structure is changeable; and
a fail-safe interface circuit which is able to control an external output from the programmable logic to a safe side,
wherein the hard macro CPU, the programmable logic, and the fail-safe interface are disposed with an interval therebetween in the field programmable gate array;
wherein the fail-safe interface circuit is provided in the programmable logic; and
wherein an instruction from the hard macro CPU to the fail-safe interface circuit is issued through a communication path in which data is able to be transmitted only from the hard macro to the programmable logic.

Assignees

• Hitachi Ltd

Inventors

• Sakata Teruaki
• Yamada Tsutomu

Classifications

• H03K19/17758

  for speeding up configuration or reconfiguration · CPC title

• B61L5/18

  Light signals; Mechanisms associated therewith, e.g. blinders · CPC title

• H03K19/17744

  for input/output signals · CPC title

• G01R31/318519 Primary

  Test of field programmable gate arrays [FPGA] · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title