Random number generation with ferroelectric random access memory

Patent metadata

Field	Value
Publication number	US-10216484-B2
Application number	US-201414301307-A
Country	US
Kind code	B2
Filing date	Jun 10, 2014
Priority date	Jun 10, 2014
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A system on chip (SoC) may include a nonvolatile ferroelectric random access memory (FRAM). A random number may be created by applying operating power to the ferroelectric random access memory (FRAM) device and reading a sequence of virgin memory locations within the FRAM device to produce the random number sequence. The sequence of virgin memory locations had previously never been written. The random number may be produced during an initial boot of the SoC, for example. Alternatively, the random number may be saved by a test station during testing of the FRAM device after fabrication of the FRAM device. A memory test of the FRAM may then be performed, after which the random number may be stored in a defined location in the FRAM.

First claim

What is claimed is:

1. A method for generating a random number based on physical characteristics of virgin cells of a ferroelectric random access memory (FRAM) array, the method comprising:
receiving, by the FRAM array of a System on a Chip (SoC), the FRAM array comprising a plurality of virgin cells, operating power; and
reading, by a processor of the SoC, the plurality of virgin cells of the FRAM array, after the FRAM array receives the operating power, to generate the random number based on spontaneous polarization of the plurality of virgin cells of the FRAM array and randomness from process variations of the plurality of virgin cells of the FRAM array, wherein the plurality of virgin cells has previously never been written.

2. The method of claim 1 , wherein the FRAM array comprises error correction logic, the method further comprising disabling error correction before reading the plurality of virgin cells.

3. The method of claim 1 , further comprising performing data encryption or signature generation using the random number as a cryptographic primitive.

4. The method of claim 1 , further comprising assigning the random number to be an identification number for the FRAM array.

5. The method of claim 1 , further comprising generating a cryptographic key using the random number as a Physically Unclonable Function (PUF).

6. The method of claim 1 , further comprising storing the random number in another non-volatile memory or in the FRAM array.

7. The method of claim 6 , further comprising:
performing a memory test of the FRAM array after storing the random number.

8. The method of claim 7 , wherein performing the memory test on the FRAM array comprises performing a built in self-test (BIST) during initial boot operation.

9. The method of claim 1 , wherein the plurality of virgin cells is scattered throughout the FRAM array.

10. The method of claim 1 , wherein the plurality of virgin cells comprises at least 256 bits.

11. The method of claim 1 , wherein the plurality of virgin cells has previously never been read.

12. A system on a chip (SoC) for generating a random number based on physical characteristics of virgin cells of a ferroelectric random access memory (FRAM) array, the SoC comprising:
the FRAM array comprising a plurality of virgin cells, the FRAM array configured to receive operating power;
a processor coupled to the FRAM array; and
a non-transitory computer readable storage meaning storing a program for execution by the processor, the program including instructions to: read the plurality of virgin cells of the FRAM array, after the FRAM array receives the operating power, to generate the random number based on spontaneous polarization of the plurality of virgin cells of the FRAM array and randomness from process variations of the plurality of virgin cells of the FRAM array, wherein the plurality of virgin cells has previously never been written.

13. The SoC of claim 12 , wherein the FRAM array comprises error correction logic, wherein the instructions further comprise instructions to disable error correction before reading the plurality of virgin cells.

14. The SoC of claim 12 , wherein the instructions further comprise instructions to perform data encryption or signature generation using the random number as a cryptographic primitive.

15. The SoC of claim 12 , wherein the instructions further comprise instructions to assign the random number to be an identification number for the FRAM array.

16. The SoC of claim 12 , wherein the instructions further comprise instructions to generate a cryptographic key using the random number as a Physically Unclonable Function (PUF.

17. The SoC of claim 12 , wherein the plurality of virgin cells is scattered throughout the FRAM array.

18. The SoC of claim 12 , wherein the plurality of virgin cells comprises at least 256 bits.

19. The SoC of claim 12 , wherein the plurality of virgin cells has previously never been read.

20. The SoC of claim 12 , wherein the instructions further comprise instructions to:
store the random number in the FRAM array; and
perform a memory test of the FRAM array after storing the random number in the FRAM array.

Assignees

• Texas Instruments Inc

Inventors

• Peeters Eric Thierry
• Kraus William Francis
• Aguilar Manuel Gilberto
• Rodriguez John Anthony

Classifications

• G11C11/225

  Auxiliary circuits · CPC title

• G11C29/04

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G06F7/588 Primary

  Random number generators, i.e. based on natural stochastic processes · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title