Storage system with read request accelerator having dynamic internal data memory allocation

Patent metadata

Field	Value
Publication number	US-10216448-B2
Application number	US-201415129480-A
Country	US
Kind code	B2
Filing date	Sep 11, 2014
Priority date	Sep 11, 2014
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

The storage system has one or more storage drives, and one or more controllers for receiving processing requests from a superior device, wherein each of the one or more controllers has a processor for executing the processing request and an accelerator, and the accelerator has multiple internal data memories and an internal control memory, wherein if the processing request is a read I/O request, it stores a control information regarding the request to the internal control memory, and reads data being the target of the relevant request from at least one storage drive out of the multiple storage drives, which is temporarily stored in the one or more said internal data memories, and transferred sequentially in order from the internal data memory already storing data to the superior device.

First claim

The invention claimed is:

1. A storage system comprising:
one or more storage drives; and
one or more controllers for receiving processing requests from a superior device;
wherein each of said one or more controllers has a processor for executing the processing requests, and an accelerator; and
wherein the accelerator has multiple internal data memories and an internal control memory,
wherein, when the accelerator receives a read Input/Output (I/O) request, the accelerator is configured to:
store a control information regarding the request in the internal control memory,
read data being the target of the read I/O request from at least one storage drive out of the multiple storage drives,
dynamically allocate one or more of said internal data memories at a timing when receiving the data being the target of the read I/O request which is read from at least one storage drive out of the one or more storage drives,
temporarily store the received data in the one or more said internal data memories, and
sequentially transfer the stored data in order from the one or more said internal data memories to the superior device.

2. The storage system according to claim 1 , wherein the accelerator is further configured to:
when dynamically allocating the one or more said internal data memories, the associate an identifier of the read I/O request to an identifier of the allocated one or more said internal data memories, and record the same in the internal control memory.

3. The storage system according to claim 2 , wherein the controller is further configured to:
instruct the accelerator to transfer the data from the one or more said internal data memories to the superior device using the identifier of the allocated one or more said internal data memories.

4. The storage system according to claim 1 , wherein the accelerator is further configured to:
when the read I/O request has an I/O length equal to or greater than a predetermined size, divide the data being the target of the I/O read request into transfer queues not greater than a capacity of one of said internal data memories, and read the data from at least one storage drive out of said one or more storage drives.

5. The storage system according to claim 1 , wherein
the accelerator is composed of an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA).

6. The storage system according to claim 5 , wherein
each of said one or more controllers has an external memory for the accelerator at an outer side of the accelerator; and
the accelerator is further configured to:
store control information related to the read I/O request in at least either the internal control memories or the external memory.

Assignees

• Hitachi Ltd

Inventors

• Nakagawa Kazushi
• Takada Masanori
• Simozono Norio

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0611

  in relation to response time · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title