Device for measuring the current flowing in an inductive load

Patent metadata

Field	Value
Publication number	US-10215782-B2
Application number	US-201615372127-A
Country	US
Kind code	B2
Filing date	Dec 7, 2016
Priority date	May 6, 2016
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A device measures the current in an inductive load using two separate current-measuring paths to detect the current in the inductive load. The inductive load is connected between first and second nodes, and the first node connected to a first voltage. The device includes first and second transistors cascaded together between the first node and a third node that is connected to a second voltage. First and second sense amplifiers measure the current in the inductive load. The first and second sense amplifiers are connected to at least one terminal of the first and second transistors. Two blocks sample and hold signals from the first and second sense amplifiers, which represent, respectively, the currents in the two separate current-measuring paths. The two currents are subtracted in a comparison node for generating an error signal that is compared with a predefined window and if outside the window a failure signal is generated.

First claim

The invention claimed is:

1. A device for measuring a current that flows in an inductive load, the device comprising a load driver device, wherein the device for measuring the current uses two separate current-measuring paths in order to detect the current that flows in the inductive load, wherein the inductive load is connected between a first node and a second node, and the first node is connected to a first voltage, the device further including a first transistor and a second transistor cascaded together and connected between the first node and a third node, wherein the third node is connected to a second voltage, said device further including a first sense amplifier and a second sense amplifier for measuring the current that flows in the inductive load, wherein said first sense amplifier is connected to at least one terminal of the first transistor and said second sense amplifier is connected to at least one terminal of the second transistor, and wherein said measurement device includes two blocks for sampling and holding the signals at output from the first sense amplifier and from the second sense amplifier, which represent, respectively, the currents that flow in said two separate current-measuring paths, wherein said two currents are subtracted in a comparison node for generating an error signal, wherein said error signal is compared in a window comparator with a predefined window and, if said error signal assumes values outside said predefined window, the device generates a failure signal.

2. The device for measuring the current according to claim 1 , wherein said first transistor and said second transistor are power N-channel MOSFET transistors.

3. The device for measuring the current according to claim 1 , wherein said first voltage is a positive voltage and said second voltage is a negative voltage or said first voltage is a negative voltage and said second voltage is a positive voltage.

4. The device for measuring the current according to claim 1 , wherein the device for measuring the current is driven by a control signal that is applied through an inverter to a gate terminal of the first transistor and applied directly to a gate terminal of the second transistor.

5. The device for measuring the current according to claim 1 , wherein the comparison between the two currents is made at a maximum current peak occurring at passage from conduction of the second transistor to conduction of the first transistor.

6. The device for measuring the current according to claim 1 , wherein the comparison between the two currents is made at a minimum current peak occurring at passage from conduction of the first transistor to conduction of the second transistor.

7. The device for measuring the current according to claim 1 , wherein the comparison between the two currents is made at a maximum current peak and the minimum current peak, and a filtering block combines and averages the values of the peaks of the two transistors to separate signal from the noise and accept or reject various types of failure.

8. The device for measuring the current according to claim 1 , wherein one sample-and-hold block processes a current sample of the first or second current while the other sample-and-hold block processes a difference between a sample of the first current through the first transistor just turned on and a previously stored sample of the second current through the second transistor.

9. The device for measuring the current according to claim 1 , wherein said first sense amplifier is connected to two terminals of the first transistor and said second sense amplifier is connected to two terminals of the second transistor, and wherein each of said sense amplifiers is configured to operate in a differential mode.

10. The device for measuring the current according to claim 1 , wherein said sample-and-hold blocks are analog memory circuits.

11. The device for measuring the current according to claim 1 , wherein said sample-and-hold blocks are sequential electronic circuits including digital memory circuits that can be obtained with digital registers, each digital register including a plurality of flip-flops.

12. The device for measuring the current according to claim 1 further comprising a block that calculates a reference value on the basis of operating conditions and a subtractor node circuit that subtracts the reference value from the error signal before the window comparator makes the decision as to whether there is or is not a failure.

13. An electronic device, comprising:
a first node configured to receive a first supply voltage a configured to be coupled to a first terminal of an inductive load;
a second node configured to be coupled to a second terminal of the inductive load;
a third node configured to receive a second supply voltage;
a switching circuit coupled to the first, second and third nodes, the switching circuit configured to couple the first node to the second node in a first operating mode and to couple the second node to the third node in a second operating mode;
a current sensing circuit coupled to the switching circuit, the current sensing circuit configured to sense a first current between the first node and the second node in the first operating mode and to sense a second current between the second node and the third node in the second operation mode;
a subtraction circuit coupled to the current sensing circuit and configured to generate an error signal based on a difference between the sensed first and second currents; and
a comparator coupled to the subtraction circuit to receive the error signal and configured to generate a failure signal based upon the error signal having a value outside a window defined by first and second threshold values.

14. The electronic device of claim 13 , wherein the switching circuit comprises:
a first transistor including a first signal node coupled to the first node and a second signal node coupled to the second node, and including a control node configured to receive a control signal; and
a second transistor including a first signal node coupled to the second node and a second signal node coupled to the third node, and including a control node configured to receive a complementary control signal, the control signal and complementary control signal having first complementary levels in the first operating mode and having second complementary levels in the second operating mode.

15. The electronic device of claim 13 , wherein the current sensing circuit comprises:
a first current sense amplifier coupled to the first transistor to sense the first current and provide a first output signal based on the sensed first current;
a second current sense amplifier coupled to the second transistor to sense the second current and provide a second output signal based on the sensed second current;
a first sample and hold circuit coupled to the first current sense amplifier and configured to sample the first output signal and provide the sampled first output signal on a first output; and
a second sample and hold circuit coupled to the second current sense amplifier and configured to sample the second output signal and provide the sampled second output signal on a second output.

16. The electronic device of claim 15 , wherein the current sensing circuit further comprises a summation circuit configured to sum the sensed first and second currents to generate an inductive load current value indicating the current through the inductive load.

17. A method of sensing a current through an inductive load coupled between first and second nodes, the method comprising

Assignees

• St Microelectronics Srl

Inventors

• Poletto Vanni
• Miglierina Riccardo
• Leone Antonio Davide
• Lecce Sergio

Classifications

• G01R31/343 Primary

  in operation · CPC title

• G01R19/1659 Primary

  to indicate that the value is within or outside a predetermined range of values (window) (G01R19/16514, G01R19/16519, G01R19/16528 and G01R19/16533 take precedence) · CPC title

• G11C27/02

  Sample-and-hold arrangements (G11C27/04 takes precedence) · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F2200/462

  the current being sensed · CPC title