Video processing apparatus and method for controlling video processing apparatus

Patent metadata

Field	Value
Publication number	US-10212439-B2
Application number	US-201515305404-A
Country	US
Kind code	B2
Filing date	Apr 20, 2015
Priority date	Apr 28, 2014
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

To achieve a reduction in circuit size without causing output leakage from a frame memory. A frame memory temporarily stores a plurality of input video signals. A plurality of encoders perform compression coding on the video signals read from the frame memory. A control unit controls the operations of writing into and reading from the frame memory. The video signals are written into the frame memory at respective frame frequencies. The video signals are read from the frame memory at a common output frame frequency. The output frame frequency is assumed to be the highest frame frequency or more of the video signals.

First claim

The invention claimed is:

1. A video processing apparatus comprising:
a frame memory configured to temporarily store a plurality of input video signals;
a control unit configured to:
write the plurality of input video signals into the frame memory at respective frame frequencies of the plurality of input video signals; and
read the plurality of input video signals from the frame memory at a common output frame frequency,
wherein the common output frame frequency is greater than or equal to a highest frame frequency of the plurality of input video signals; and

a plurality of encoders configured to execute, based on a reference signal at the common output frame frequency, a compression coding operation on the plurality of input video signals that are read from the frame memory.

2. The video processing apparatus according to claim 1 , further comprising: a sync status unit configured to monitor at least one frame position and at least one line position of the plurality of input video signals,
wherein the control unit is further configured to:
write the plurality of input video signals into the frame memory based on the monitoring by the sync status unit; and
read the plurality of input video signals from the frame memory based on the monitoring of the sync status unit.

3. The video processing apparatus according to claim 2 , wherein the control unit is further configured to:
issue a write instruction, within a first frame, for a second frame at a timing of the common output frame frequency; and
issue a single write instruction in the first frame for a respective video signal of the plurality of input video signals.

4. The video processing apparatus according to claim 2 , wherein the control unit is further configured to:
issue a read instruction at a timing of the common output frame frequency; and
prevent issue of the read instruction based on a determination that reading exceeds writing for a respective video signal of the plurality of input video signals.

5. The video processing apparatus according to claim 1 , wherein the plurality of encoders are further configured to stop the compression coding operation in an output frame period in which a video signal of the plurality of input video signals is not read from the frame memory.

6. The video processing apparatus according to claim 5 , wherein the plurality of encoders are further configured to stop the compression coding operation in the output frame period based on a disable signal.

7. The video processing apparatus according to claim 6 , further comprising a timing generator configured to generate the disable signal.

8. The video processing apparatus according to claim 5 , wherein the plurality of encoders are further configured to stop the compression coding operation in the output frame period based on a stop of a supply of the reference signal.

9. The video processing apparatus according to claim 1 , further comprising: an oscillator configured to generate the reference signal at the common output frame frequency.

10. The video processing apparatus according to claim 1 , further comprising: a port configured to input the reference signal at the common output frame frequency.

11. The video processing apparatus according to claim 1 , wherein the control unit comprises:
a first que to save write instructions to write the plurality of input video signals into the frame memory; and
a second que to save read instructions to read the plurality of input video signals from the frame memory.

12. The video processing apparatus according to claim 1 , further comprising a selection unit configured to transmit the plurality of input video signals subjected to the compression coding operation to a storage device in a time division manner.

13. A method for controlling a video processing apparatus comprising:
temporarily storing a plurality of input video signals in a frame memory;
writing the plurality of input video signals into the frame memory at respective frame frequencies;
reading the plurality of input video signals from the frame memory at a common output frame frequency, wherein the common output frame frequency is greater than or equal to a highest frame frequency of the plurality of input video signals; and
executing, based on a reference signal at the common output frame frequency, a compression coding process on the plurality of input video signals that are read from the frame memory.

Assignees

• Sony Corp

Inventors

• Kojima Kentaro
• Chiba Nobuhiro
• Seto Hiroaki
• Ozawa Shusuke
• Sato Junya
• Koyabu Kyohei

Classifications

• H04N19/90

  using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals · CPC title

• H04N5/073

  for mutually locking plural sources of synchronising signals, e.g. studios or relay stations · CPC title

• H04N19/426 Primary

  using memory downsizing methods · CPC title

• H04N19/427 Primary

  Display on the fly, e.g. simultaneous writing to and reading from decoding memory · CPC title