Semiconductor memory device and a chip stack package having the same

Patent metadata

Field	Value
Publication number	US-10211123-B2
Application number	US-201715678197-A
Country	US
Kind code	B2
Filing date	Aug 16, 2017
Priority date	Dec 15, 2016
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A semiconductor memory device includes an integrated circuit (IC) chip structure, wherein the IC chip includes a substrate, a memory cell disposed on the substrate, and a local well disposed on the substrate, wherein a conductivity type of the local well is different from a conductivity type of the substrate, a wiring stack structure disposed on the IC chip structure, wherein the wiring stack structure includes a signal transfer pattern connected to the memory cell through a signal interconnector, and a thermal dispersion pattern connected to the local well through a thermal interconnector, and a heat transfer structure connected to the thermal dispersion pattern for transferring heat to the thermal dispersion pattern from a heat source.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
an integrated circuit (IC) chip structure,
wherein the IC chip structure includes:
a substrate;
a memory cell disposed on the substrate; and
a local well disposed on the substrate, wherein a conductivity type of the local well is different from a conductivity type of the substrate;

a wiring stack structure disposed on the IC chip structure, wherein the wiring stack structure includes a signal transfer pattern connected to the memory cell through a signal interconnector, and a thermal dispersion pattern connected to the local well through a thermal interconnector;
a heat transfer structure connected to the thermal dispersion pattern for transferring heat to the thermal dispersion pattern from a heat source; and
at least one heat bump between the heat source and the thermal interconnector.

2. The semiconductor memory device of claim 1 , wherein each of the signal transfer pattern and the thermal dispersion pattern includes a metal pattern, wherein the metal pattern of the signal transfer pattern and the metal pattern of the thermal dispersion pattern have a same stack structure, and wherein the signal interconnector and the thermal interconnector includes a same metal via structure.

3. The semiconductor memory device of claim 1 , wherein the at least one heat bump is in contact with the heat source and the thermal interconnector.

4. The semiconductor memory device of claim 1 , wherein the heat transfer structure includes:
a heat transfer circuit connected with the at least one heat bump and the thermal dispersion pattern.

5. The semiconductor memory device of claim 4 , wherein the heat transfer circuit includes:
a first heat transfer line connected to the at least one heat bump and a second heat transfer line connected to the thermal dispersion pattern;
a first bridge via connected to the first heat transfer line and a second bridge via connected to the second heat transfer line; and
a bridge line connected to the first and second bridge vias.

6. A semiconductor memory device comprising:
an integrated circuit (IC) chip structure,
wherein the IC chip structure includes:
a substrate; and
a memory cell disposed on the substrate;

a wiring stack structure disposed on the IC chip structure, wherein the wiring stack structure includes a signal transfer pattern connected to the memory cell through a signal interconnector, and a thermal dispersion pattern connected to the semiconductor substrate through a thermal interconnector, wherein the signal interconnector transfers operating signals to the memory cell;
a heat spreader disposed on the substrate and connected to the thermal dispersion pattern such that heat is dissipated from the thermal dispersion pattern through the heat spreader; and
a heat transfer structure connected to the thermal dispersion pattern and transferring the heat from a heat source to the thermal dispersion pattern, wherein the heat transfer structure includes:
at least one heat bump connected with the heat source.

7. The semiconductor memory device of claim 6 , further comprising a heat column, wherein the heat column is connected with the heat spreader and the thermal dispersion pattern through the substrate.

8. The semiconductor memory device of claim 6 , wherein the heat transfer structure includes:
a heat transfer circuit connected with the heat bump and the thermal dispersion pattern.

9. A chip stack package comprising:
a circuit board including at least one conductive pattern;
a first die mounted on the circuit board, the first die including a first chip and at least one second chip that generates more heat than the first chip, wherein a portion of the first die that is heated from the at least one second chip is a hot spot; and
a second die stacked on the first die and connected to the first die,
wherein the second die includes:
an integrated circuit (IC) chip structure on which data is stored;
a wiring stack structure, the wiring stack structure including a signal transfer pattern connected to the IC chip structure for transferring operating signals to the IC chip structure, and a thermal dispersion pattern that disperses the heat from the hot spot; and
a heat transfer structure for transferring the heat from the hot spot to the thermal dispersion pattern.

10. The chip stack package of claim 9 , wherein the IC chip structure includes:
a substrate;
a memory cell disposed on the substrate; and
a local well disposed on the substrate, wherein a conductivity type of the local well is different from a conductivity type of the substrate,
wherein the wiring stack structure is disposed on the IC chip structure, wherein the wiring stack structure includes a signal transfer pattern connected to the memory cell through a signal interconnector, and a thermal dispersion pattern connected to the local well through a thermal interconnector, and
wherein the heat transfer structure includes at least one heat bump contacting the hot spot, and a heat transfer circuit connected to the thermal dispersion pattern and to the at least one heat bump.

11. The chip stack package of claim 10 , further comprising a lateral heat spreader disposed on at least one side of the second die,
wherein the lateral heat spreader is connected to the heat transfer circuit such that the heat of the hot spot is dissipated through the lateral heat spreader.

12. The chip stack package of claim 9 , wherein the IC chip structure includes:
a substrate;
a memory cell disposed on the substrate; and
a heat column penetrating the substrate,
wherein the wiring stack structure is stacked on the IC chip structure, wherein the wiring stack structure includes a signal transfer pattern connected to the memory cell through a signal interconnector, and a thermal dispersion pattern connected to the local well through a thermal interconnector, and
wherein the heat transfer structure includes at least one heat bump contacting the hot spot, and a heat transfer circuit connected to the thermal dispersion pattern and to the at least one heat bump.

13. The chip stack package of claim 12 , wherein, when the substrate includes a first surface and a second surface opposite to the first surface, and the memory cell is disposed on the first surface, the second die further includes a heat spreader disposed on the second surface, and
wherein the heat spreader contacts the heat column to dissipate heat from the thermal dispersion pattern.

14. The chip stack package of claim 9 , wherein the first die is connected to the circuit board by using a bonding wire, and
wherein the second die is connected to the first die by using a conductive bump structure.

15. The chip stack package of claim 9 , wherein the first chip of the first die includes a central process unit (CPU) or a graphic processing unit (GPU), and the second die includes a memory device into which data is stored in response to signals from the CPU or the GPU.

16. A semiconductor memory device comprising:
an integrated circuit (IC) chip structure,
wherein the IC chip structure includes:
a substrate;
a memory cell disposed on the substrate; and
a local well disposed on the substrate, wherein a conductivity type of the local well is different from a conductivity type of the substrate;

a wiring stack structure disposed on the IC chip structure, wherein the wiring stack structure includes a signal transfer pattern, a thermal dispersion pattern, a first insulation layer, and a second insulation layer stacked on the first insulation layer,
wherein the signal tra

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Jong-Pil

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722 Primary

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title