Sleep signal stitching technique

Patent metadata

Field	Value
Publication number	US-10210303-B2
Application number	US-201715418613-A
Country	US
Kind code	B2
Filing date	Jan 27, 2017
Priority date	Jan 27, 2017
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

Various implementations described herein are directed to an apparatus having a receiver module that receives a floorplan of an integrated circuit having power gates, an obstruction, and a control pin for providing a sleep signal. The apparatus can include an identifier module that identifies where the obstruction interrupts a sequence of the power gates, organizes the sequence of the power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first segment and the second segment. The apparatus can include a stitcher module that performs a sleep signal stitching for the integrated circuit by distributing the sleep signal from the control pin to the power gates that include each power gate in each of the first segment, the second segment, and the third segment.

First claim

What is claimed is:

1. An apparatus, comprising:
a receiver module that receives a floorplan of an integrated circuit having multiple power gates, an obstruction, and a control pin for providing a sleep signal;
an identifier module that identifies where the obstruction interrupts a sequence of the multiple power gates, organizes the sequence of the multiple power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first segment and the second segment, wherein the third segment is routed around the obstruction; and
a stitcher module that performs a sleep signal stitching for the integrated circuit by distributing the sleep signal from the control pin to the multiple power gates that include each power gate in each segment of the first segment, the second segment, and the third segment.

2. The apparatus of claim 1 , wherein the floorplan comprises a collection of chains, and wherein each chain in the collection of chains comprises a collection of power gates coupled to the control pin.

3. The apparatus of claim 1 , wherein the floorplan comprises the obstruction as part of a collection of one or more non-overlapping obstructions.

4. The apparatus of claim 1 , wherein the obstruction comprises a rectilinear obstruction.

5. The apparatus of claim 1 , wherein the sequence of the multiple power gates comprises a linear sequence of the multiple power gates arranged in one or more vertical columns, and wherein the obstruction interrupts the linear sequence of the multiple power gates.

6. The apparatus of claim 1 , wherein the third segment comprises the multiple power gates in a relocated position around the obstruction.

7. The apparatus of claim 1 , wherein a distance between two points in the floorplan is measured using a Steiner metric, and wherein if the obstruction is between the two points, then the distance is computed by following edges of the obstruction.

8. The apparatus of claim 1 , wherein the stitcher module distributes the sleep signal from the control pin to the multiple power gates by coupling the control pin to each power gate of the multiple power gates to thereby provide the sleep signal to said each power gate.

9. The apparatus of claim 1 , wherein each power gate of the multiple power gates is a cell with at least two pins including a sleep input pin and a sleep output pin, and wherein the sleep input pin of said each power gate receives the sleep signal from the control pin or from the sleep output pin of another power gate of the multiple power gates.

10. The apparatus of claim 1 , wherein the obstruction is defined by a hard macro that represents a component of the integrated circuit having a core, a memory, a double data rate (DDR) unit, or a power management unit.

11. The apparatus of claim 1 , wherein arrival of the sleep signal at each power gate of the multiple power gates switches each power gate to an active state which then supplies power to rails from which standard cells (SC) of the integrated circuit derive their power.

12. A method, comprising:
receiving a floorplan of an integrated circuit having multiple power gates, an obstruction, and a control pin for providing a sleep signal;
identifying where the obstruction interrupts a sequence of the multiple power gates;
organizing the sequence of the multiple power gates into a column;
dividing the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first segment and the second segment, wherein the third segment is routed around the obstruction by modifying a position of the multiple power gates in the third segment so as to avoid the obstruction; and
performing a sleep signal stitching for the integrated circuit by distributing the sleep signal from the control pin to the multiple power gates that include each power gate in each segment of the first segment, the second segment, and the third segment.

13. The method of claim 12 , wherein the obstruction comprises a rectilinear region in a form of a rectangle or an L-shape.

14. The method of claim 12 , wherein the sequence of the multiple power gates comprises a linear sequence of the multiple power gates arranged in one or more vertical columns, and wherein the obstruction interrupts the linear sequence of the multiple power gates.

15. The method of claim 12 , wherein modifying a position of the multiple power gates in the third segment comprises relocating the position of the multiple power gates in the third segment around the obstruction.

16. The method of claim 12 , wherein a distance between two points in the floorplan is measured using a Steiner metric, and wherein if the obstruction is between the two points, then the distance is computed by following edges of the obstruction.

17. The method of claim 12 , wherein the distributing the sleep signal from the control pin to the multiple power gates comprises coupling the control pin to each power gate of the multiple power gate to thereby provide the sleep signal to said each power gate.

18. The method of claim 12 , wherein each power gate of the multiple power gate is a cell with at least two pins including a sleep input pin and a sleep output pin, and wherein the sleep input pin of said each power gate receives the sleep signal from the control pin or from the sleep output pin of another power gate of the multiple power gates.

19. The method of claim 12 , wherein the obstruction is defined by a hard macro that represents a component of the integrated circuit having a core, a memory, a double data rate (DDR) unit, or a power management unit.

20. A non-transitory computer-readable medium having stored thereon a plurality of computer-executable instructions that, when executed by a computer, cause the computer to:
receive a floorplan of an integrated circuit having multiple power gates, an obstruction, and a control pin for providing a sleep signal;
identify where the obstruction interrupts a sequence of the multiple power gates;
organize the sequence of the multiple power gates into a column;
divide the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first segment and the second segment, wherein the third segment is routed around the obstruction by modifying a position of the multiple power gates in the third segment so as to avoid the obstruction; and
perform a sleep signal stitching for the integrated circuit by distributing the sleep signal from the control pin to the multiple power gates that include each power gate in each segment of the first segment, the second segment, and the third segment.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Rao Ravindra Narayana
• Frederick Jr Marlin Wayne
• Delk Karen Lee
• Creaser Stefan Charles

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5077

  Physics · mapped topic