System and methods for simulating a circuit design

Patent metadata

Field	Value
Publication number	US-10210294-B1
Application number	US-201514795624-A
Country	US
Kind code	B1
Filing date	Jul 9, 2015
Priority date	Jul 9, 2015
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A method of enabling a simulation of a circuit design is described. The method comprises generating, using a computer, an initial representation of the circuit design; simulating the circuit design using the initial representation by driving input signals to the circuit design based upon a simulation event listing; capturing event data associated with a plurality of timestamps in a first file while simulating the circuit design; identifying a plurality of events associated with a timestamp of a plurality of timestamps; reordering events of the plurality of associated with the timestamp; and generating a replay module used to drives input signals to the circuit design. A system for enabling a simulation of a circuit design is also described.

First claim

What is claimed is:

1. A method of enabling a simulation of a circuit design, the method comprising:
generating, using a computer, an initial representation of the circuit design;
simulating the circuit design using the initial representation by driving first input signals to the circuit design of a device under test based upon a simulation event listing;
capturing event data associated with a plurality of timestamps in a first file while simulating the circuit design;
identifying a plurality of events associated with a timestamp of a plurality of timestamps;
reordering events of the plurality of events associated with the timestamp of the plurality of time stamps by providing a delay between a first event and a second event of the plurality of events associated with the time stamp, wherein providing a delay between the first event and the second event prevents false negatives by providing an order to the first event and the second event; and
generating a module having the reordered events used to drive second input signals to the circuit design of the device under test.

2. The method of claim 1 further comprising generating an ordered input listing that indicates an order of the identified plurality of events associated with the timestamp.

3. The method of claim 2 further comprising decomposing the simulation event listing using the ordered input listing, wherein the module is generated based upon the decomposed simulation event listing.

4. The method of claim 1 further comprising simulating the circuit design a second time using the module.

5. The method of claim 4 further comprising capturing event data to a second file during the second simulating.

6. The method of claim 5 further comprising determining whether or not the event data in the first file matches the event data in the second file.

7. The method of claim 6 wherein simulating the circuit design a second time comprises simulating the circuit design during a design implementation process selected from a group consisting of synthesis, optimization, placement, and routing.

8. A method of enabling the simulation of a circuit design, the method comprising:
generating, using a computer, an initial representation of the circuit design;
simulating the circuit design using the initial representation by driving input signals to the circuit design of a device under test based upon a simulation event listing;
capturing events associated with a plurality of timestamps in a first file while simulating the circuit design;
identifying a plurality of events associated with a timestamp of a plurality of timestamps;
scheduling a first event of the plurality of events after the timestamp;
inserting a new timestamp between the first event and a second event of the plurality of events, wherein inserting a new timestamp between the first event and the second event prevents false negatives by providing an order to the first event and the second event; and
scheduling a second event of the plurality of events after the new timestamp.

9. The method of claim 8 further comprising generating an ordered input listing that indicates an order of the identified plurality of events associated with the timestamp.

10. The method of claim 9 further comprising decomposing the simulation event listing using the ordered input listing, and generating a module based upon the decomposed simulation event listing.

11. The method of claim 10 further comprising simulating the circuit design a second time using the module and capturing event data to a second file.

12. The method of claim 11 wherein simulating the circuit design a second time comprises simulating the circuit design during a design implementation process selected from a group consisting of synthesis, optimization, placement, and routing.

13. The method of claim 8 further comprising dividing the events associated with the timestamp as early events and late events.

14. The method of claim 8 wherein identifying a plurality of events associated with a timestamp of a plurality of timestamps comprises identifying a plurality of events between the timestamp and a next timestamp, wherein the new timestamp is inserted between the timestamp and the next timestamp.

15. A system for enabling a simulation of a circuit design, the system comprising:
a processor;
a memory arrangement coupled to the processor and configured with program code, the program code, when executed by the processor, causing the processor to perform operations including:
simulating the circuit design using an initial representation by driving first input signals to the circuit design of a device under test based upon a simulation event listing;
capturing events associated with a plurality of timestamps while simulating the circuit design;
identifying events associated with a timestamp of a plurality of timestamps;
reordering the events associated with the timestamp of the plurality of time stamps by providing a delay between a first event and a second event of the plurality of events associated with the time stamp, wherein providing a delay between the first event and the second event prevents false negatives by providing an order to the first event and the second event; and
generating a module used to drive second input signals to the circuit design of the device under test.

16. The system of claim 15 , the operations further including generating an ordered input listing that indicates an order of the identified events associated with the timestamp.

17. The system of claim 16 , the operations further including decomposing the simulation event listing using the ordered input listing, wherein the module is generated based upon the decomposed simulation event listing.

18. The system of claim 15 , the operations further including simulating the circuit design a second time using the module, and capturing event data to a second file.

19. The system of claim 18 , the operations further including determining whether or not the event data in the first file matches the event data in the second file.

20. The system of claim 18 , wherein simulating the circuit design a second time comprises simulating the circuit design during a design implementation process selected from a group consisting of synthesis, optimization, placement, and routing.

Assignees

• Xilinx Inc

Inventors

• Corbett Kyle

Classifications

• G01R31/318364

  as a result of hardware simulation, e.g. in an HDL environment (computer-aided simulation of circuits G06F30/3308) · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G01R31/318342

  by preliminary fault modelling, e.g. analysis, simulation · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title