Communication via a memory interface

Patent metadata

Field	Value
Publication number	US-10209922-B2
Application number	US-201514806788-A
Country	US
Kind code	B2
Filing date	Jul 23, 2015
Priority date	Aug 24, 2011
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.

First claim

What is claimed is:

1. A module, comprising:
a memory interface configured to interface with a memory controller, the memory interface including a memory data interface and a memory command/address interface, the memory command/address interface to receive memory controller read commands and first column addresses to read data from the first column addresses of the module and to receive memory controller write commands and second column addresses to write data to the second column addresses of the module, the data to be communicated via the memory data interface; and,
the module to execute module commands written to the module via the memory data interface from the memory controller using the memory controller write commands, the write commands to be addressed to a first plurality of column addresses in a command port of the module, the memory controller to read information associated with the module commands from a second plurality of column addresses in a status port of the module.

2. The module of claim 1 , wherein the memory controller reads the second plurality of column addresses to determine which of the module commands written to the first plurality of column addresses have been received by the module.

3. The module of claim 1 , wherein the memory controller reads the second plurality of column addresses to determine which of the module commands written to the first plurality of column addresses have been performed by the module.

4. The module of claim 1 , wherein the memory controller reads the second plurality of column addresses in response to at least one DMA instruction processed by a CPU coupled to the memory controller.

5. The module of claim 4 , wherein the module includes a processor and a memory, and wherein the second plurality of column addresses are read in response to the at least one DMA instruction directly from the memory and not read from the memory via the processor.

6. The module of claim 1 , wherein the memory controller writes the first plurality of column addresses in response to at least one DMA instruction processed by a CPU coupled to the memory controller.

7. The module of claim 6 , wherein the module includes a processor and a memory, and wherein the first plurality of column addresses are written in response to the at least one DMA instruction by the memory controller directly to the memory and not written to the memory via the processor.

8. A dual-inline memory module (DIMM), comprising:
a parallel module interface configured to interface with a memory controller of a host system, the parallel module interface including a memory data interface and a memory command/address interface, the memory command/address interface to receive memory controller read commands and first column addresses to read data from the first column addresses of the DIMM and to receive memory controller write commands and second column addresses to write data to the second column addresses of the DIMM, the data to be communicated via the memory data interface, the host to provide, to the memory controller for provision to the module, first data comprising a plurality of module commands to be executed by the module and to be written, via the memory data interface, to a first memory address range that functions as a command port for the DIMM using the memory controller write commands, and the host to read via the memory controller, from a second memory address range that functions as a status port for the DIMM, second data comprising indicators associated with the plurality of commands.

9. The module of claim 8 , wherein the host provides the first data in response to a DMA operation performed by the host.

10. The module of claim 8 , wherein the host reads the second data in response to a DMA operation performed by the host.

11. The module of claim 10 , wherein the second data comprises a plurality of entries each corresponding to one of the plurality of commands stored to the command port.

12. The module of claim 8 , wherein the module includes a processor and a memory, and wherein the first data is to be written to the first memory address range of the module directly to the memory in response to at least one DMA operation performed by the host and not written to the memory via the processor.

13. The module of claim 8 , wherein the module includes a processor and a memory, and wherein the second data is to be read from the second memory address range of the module directly from the memory in response to at least one DMA operation performed by the host and not read from the memory via the processor.

14. The module of claim 8 , further comprising:
a processor;
a memory associated with the first memory address range and the second memory address range, wherein the first data is to be written to the first memory address range of the module directly to the memory in response to a first DMA operation performed by the host, and wherein the second data is to be read from the second memory address range of the module directly from the memory in response a second one DMA operation performed by the host, the first DMA operation and the second DMA operation not using the processor to access to the memory.

15. A system, comprising:
a central processing unit (CPU) with a memory controller configured to direct delivery of module commands from the CPU to module memory using parallel data channels; and,
a dual-inline memory module (DIMM) configured to receive the module commands from the CPU, including:
a parallel module interface configured to interface with a memory controller of the system, the parallel module interface including a memory data interface and a memory command/address interface, the memory command/address interface to receive memory controller read commands and first column addresses to read data from the first column addresses of the DIMM and to receive memory controller write commands and second column addresses to write data to the second column addresses of the DIMM, the data to be communicated via the memory data interface, the host to provide, to the memory controller for provision to the module, first data comprising a plurality of module commands to be executed by the module and to be written, via the memory data interface, to a first memory address range of the module that functions as a command port for the DIMM using the memory controller write commands, and to read, from a second memory address range of the module that functions as a status port for the DIMM, second data comprising indicators associated with the plurality of module commands; and,
a processor to execute the module commands and to provide the second data.

16. The system of claim 15 , wherein the second data includes entries that indicate whether an associated module command written to the command port has been executed by the module.

17. The system of claim 15 , wherein the second data includes entries that indicate whether an associated module command written to the command port has been received by the module.

18. The system of claim 15 , wherein the first data is provided in response to a DMA instruction performed by the CPU and the second data includes an entry that indicates whether the DMA instruction has completed writing the first data.

19. The system of claim 15 , wherein the first data is provided in response to a first DMA operation performed by the CPU and the second data is read in response to a second DMA operation performed by the CPU.

20. The system of claim 19 , wherein the first data is provided to a memory on the modu

Assignees

• Rambus Inc

Inventors

• Gopalakrishnan Liji
• Fruchter Vlad
• Lai Lawrence
• Batra Pradeep
• Woo Steven C
• Ellis Wayne Frederick

Classifications

• G06F13/1668

  Details of memory controller · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F12/06

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• G06F13/1626 Primary

  by reordering requests · CPC title