Graphics processing system and power gating method thereof

Patent metadata

Field	Value
Publication number	US-10209758-B2
Application number	US-201415510261-A
Country	US
Kind code	B2
Filing date	Dec 12, 2014
Priority date	Dec 12, 2014
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A graphics processing system and power gating method thereof, the graphics processing system comprising: a graphics processing unit (GPU), a bus interface and a power management unit (PMU), the GPU comprising a control circuit and a plurality of partitions; the method includes: when the bus interface receives an external graphics command, utilizing the PMU to turn on a power supply of the control circuit; subsequently utilizing the control circuit to turn on power supplies of one or more partitions of the plurality of partitions corresponding to the external graphics command; when then control circuit detects any one of the plurality of partitions is in an idle state, utilizing the control circuit to turn off the power supply of the partition in the idle state; when the bus interface detects the plurality of partitions are in a full idle state, utilizing the bus interface to turn off the power supply of the control circuit via the PMU; and when the PMU turns off the power supply of the control circuit, the control circuit may also turn off the power supplies of the plurality of the partitions.

First claim

What is claimed is:

1. A graphics processing system, comprising:
a bus interface, configured to receive an external graphics processing command;
a graphics processing unit, comprising:
a plurality of partitions; and
a control circuit configured to control a power state of each partition and detect an idle state of each partition; and
a power management unit configured to control power to the control circuit of the graphics processing unit,
wherein the bus interface is external to the graphics processing unit,
wherein when the bus interface has received the external graphics processing command, the bus interface informs the power management unit to turn on the power to the control circuit, and the control circuit turns on the power to one or more of the partitions corresponding to the external graphics processing command after the control circuit analyzes the external graphics processing command,
wherein the control circuit turns off the power to the partitions in the idle state when the control circuit has detected that one of the partitions is in the idle state,
wherein when the bus interface has detected that the partitions are in a full idle state, the bus interface turns off the power to the control circuit via the power management circuit.

2. The graphics processing unit as claimed in claim 1 , wherein the control circuit is in an always-on state after the power management unit turns on the power to the control circuit, and the control circuit further turns off the power to the partitions when the power management unit turns off the power to the control circuit.

3. The graphics processing unit as claimed in claim 2 , wherein the control circuit comprises a first detection circuit for turning on the power to one or more of the partitions after analyzing the external graphics processing command.

4. The graphics processing unit as claimed in claim 1 , wherein the graphics processing unit comprises a thermal sensor for detecting temperature information of the graphics processing unit.

5. The graphics processing unit as claimed in claim 4 , wherein the control circuit generates a full idle state signal according to the temperature information from the thermal sensor and an idle state signal from each partition.

6. The graphics processing unit as claimed in claim 1 , wherein the bus interface comprises a second detection circuit, and the second detection circuit is always-on for simultaneously receiving the external graphics processing command and informs the power management unit to turn on the power to the control circuit.

7. The graphics processing unit as claimed in claim 6 , wherein the second detection circuit determines whether the graphics processing unit is in the full idle state according to a full idle state signal from the control circuit.

8. A power gating method for use in a graphics processing system, wherein the graphics processing system comprises a graphics processing unit, a bus interface, and a power management unit, and the graphics processing unit comprises a control circuit and a plurality of partitions, the method comprising:
utilizing the power management unit to turn on power to the control circuit when the bus interface, which is external to the graphics processing unit, has received an external graphics processing command;
utilizing the control circuit to turn on power to the partitions corresponding to the external graphics processing command after utilizing the control circuit to analyze the external graphics processing command;
utilizing the control circuit to turn off the power to the partitions in the idle state when the control circuit has detected that one of the partitions is in an idle state; and
utilizing the bus interface to turn off the power to the control circuit via the power management unit when the bus interface has detected that the partitions are in a full idle state.

9. The method as claimed in claim 8 , wherein the graphics processing unit comprises a thermal sensor for detecting temperature information of the graphics processing unit.

10. The method as claimed in claim 9 , further comprising:
utilizing the control circuit to generate a full idle state signal according to the temperature information from the thermal sensor and an idle state signal from each partition.

11. The method as claimed in claim 10 , wherein the bus interface comprises a detection circuit, and the method further comprises:
utilizing the detection circuit to determine whether the graphics processing unit is in the full idle state according to the full idle state signal from the control circuit.

12. The method as claimed in claim 8 , wherein the control circuit is in an always-on state after the power management unit turns on the power to the control circuit, and the control circuit further turns off the power to the partitions when the power management unit turns off the power to the control circuit.

13. A power gating method for use in a graphics processing system, wherein the graphics processing system comprises a graphics processing unit and a bus interface, the graphics processing unit comprises a control circuit and a plurality of partitions, the method comprising:
turning on power of the control circuit by the bus interface when the bus interface external to the graphics processing unit receives an external graphics processing command, wherein the control circuit is in an always-on state until a full idle state is detected;
turning on power of the partitions associated with the external graphics processing command by the control circuit; and
turning off the power of the partitions being detected in an idle state by the control circuit.

14. The method as claimed in claim 13 , further comprising:
generating a full idle state signal according to a temperature information from a thermal sensor and an idle state signal from each partition.

15. The method as claimed in claim 14 , wherein the bus interface comprises a detection circuit to determine whether the graphics processing unit is in the full idle state.

16. The method as claimed in claim 13 , further comprising a power management unit which is independent of the graphics processing unit to turn on or turn off the power of the control circuit.

17. The method as claimed in claim 13 , wherein the bus interface comprises an always-on detection circuit for turning on the power of the control circuit no matter a power status of the control circuit.

18. The method as claimed in claim 13 , further comprising analyzing the external graphics processing command before turning on power of the partitions associated with the external graphics processing command.

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Gu Deming
• Hong Zhou

Classifications

• G06F1/32

  Means for saving power · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• Y02D10/10

  Cross-Sectional Technologies · mapped topic

• G06T2200/28

  involving image processing hardware · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title