Decoding method, apparatus, and algorithm for nonbinary LDPC codes

Patent metadata

Field	Value
Publication number	US-10205468-B2
Application number	US-201514686629-A
Country	US
Kind code	B2
Filing date	Apr 14, 2015
Priority date	Apr 14, 2014
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

Provided is a method for decoding a non-binary (NB) low density parity check (LDPC) code at a user equipment (UE) that implements at least one variable nodes that receive a received signal of a wireless channel and deliver an input message to a check node and the check node that checks the input message and outputs an output message. The method includes receiving at least one input messages, generating a temporary vector by using the at least one input messages, searching for an element having a dominant value by checking the temporary vector, generating a configuration set, which is a check target, by using the element having the dominant value, and generating the output message by performing comparison with respect to the generated configuration set.

First claim

What is claimed is:

1. A method for reducing memory usage in implementing at least one variable node and a check node at a user equipment (UE), the UE including a processor, a transceiver and a memory, the method comprising:
receiving, by the transceiver, a signal from a wireless channel;
receiving, by the processor, at least one input message:
generating, by the processor, a temporary vector by using the at least one input message;
storing the temporary vector in a memory;
determining, by the processor, a dominant value based on the temporary vector;
storing the dominant value in the memory;
determining, by the processor, a configuration set including an element having the dominant value;
generating, by the processor, an output message by performing a comparison with respect to the configuration set including the element having the stored dominant value;
determining, by the processor, a next-order dominant value based on the output message;
storing the next-order dominant value in the memory;
determining, by the processor, a new configuration set including an element having the stored next-order dominant value; and
updating, by the processor, the output message by performing a comparison with respect to the new configuration set including the element having the stored next-order dominant value,
wherein a number of combinations of configuration sets which are check targets and a number of comparison operations are determined based on a number of the dominant values.

2. The method of claim 1 , wherein generating the configuration set comprises generating combinations of the element having the dominant value and remaining elements of the temporary vector as the configuration set.

3. The method of claim 1 , wherein the input message and the output message are vectors having a length of q.

4. The method of claim 3 , wherein determining the new configuration set comprises generating combinations of the element having the next-order dominant value and remaining elements of the output message as the new configuration set.

5. The method of claim 4 , wherein the element having the dominant value is excluded from the remaining elements of the output message.

6. The method of claim 1 , further comprising:
storing the element having the dominant value of the temporary vector.

7. The method of claim 3 , wherein a number of update operations with respect to the output message is changed.

8. The method of claim 1 , wherein the input message and the output message are vectors having a length of q, and generating the temporary vector comprises:
comparing the at least one input message to search for an element having a dominant value; and
generating the temporary vector including the element having the dominant value.

9. The method of claim 1 , wherein the input message and the output message are vectors having a length of q, and generating the temporary vector comprises:
generating a temporary configuration set from as many input messages as a degree of the check node among the at least one input message; and
checking the generated temporary configuration set to generate the temporary vector.

10. A user equipment (UE) apparatus implementing at least one variable nodes and a check node, the UE apparatus comprising:
a transceiver configured to receive a signal from a wireless channel;
a memory; and
a processor configured to:
receive, via the transceiver, at least one input message;
generate a temporary vector by using the at least one input message;
store the temporary vector in the memory;
determine a dominant value based on the temporary vector;
store the dominant value in the memory;
determine a configuration set including an element having the stored dominant value;
generate an output message by performing a comparison with respect to the configuration set including the element having the stored dominant value;
determine a next-order dominant value based on the output message;
store the next-order dominant value in the memory;
determine a new configuration set including an element having the stored next-order dominant value; and
update the output message by performing a comparison with respect to the new configuration set including the element having the stored next-order dominant value,
wherein a number of combinations of configuration sets which are check targets and a number of comparison operations are determined based on a number of the dominant values.

11. The UE apparatus of claim 10 , wherein the processor is configured to generate combinations of the element having the dominant value and remaining elements of the temporary vector as the configuration set.

12. The UE apparatus of claim 10 , wherein the input message and the output message are vectors having a length of q.

13. The UE apparatus of claim 12 , wherein the processor is configured to generate combinations of the element having the next-order dominant value and remaining elements of the output message as the new configuration set.

14. The UE apparatus of claim 13 , wherein the element having the dominant value is excluded from the remaining elements of the output message.

15. The UE apparatus of claim 10 , wherein the processor is configured to store the element having the dominant value of the temporary vector.

16. The UE apparatus of claim 12 , wherein the processor is configured to change a number of update operations with respect to the output message.

17. The UE apparatus of claim 10 , wherein the input message and the output message are vectors having a length of q, and
the processor is configured to:
compare the at least one input message to search for an element having a dominant value; and
generate the temporary vector including the element having the dominant value.

18. The UE apparatus of claim 10 , wherein the input message and the output message are vectors having a length of q, and
the processor is configured to:
generate a temporary configuration set from as many input messages as a degree of the check node among the at least one input message; and
check the generated temporary configuration set to generate the temporary vector.

19. The method of claim 1 , wherein the dominant value is a larger value for a probability value and a smaller value for a relative value.

20. The UE apparatus of claim 10 , wherein the dominant value is a larger value for a probability value and a smaller value for a relative value.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Seok-Ki
• Yang Kyeong-Cheol
• Kim Sang-Min
• Park Woo-Myoung
• Sagong Min
• Lim Chi-Woo
• Hong Sung-Nam

Classifications

• H03M13/6577

  Representation or format of variables, register sizes or word-lengths and quantization · CPC title

• H03M13/6502

  Reduction of hardware complexity or efficient processing · CPC title

• H03M13/1117

  using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule · CPC title

• H03M13/1171 Primary

  Parity-check or generator matrices with non-binary elements, e.g. for non-binary LDPC codes · CPC title