Run-time output clock determination

Patent metadata

Field	Value
Publication number	US-10205458-B2
Application number	US-201715644632-A
Country	US
Kind code	B2
Filing date	Jul 7, 2017
Priority date	Jul 1, 2011
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

First claim

What is claimed is:

1. A method of operation within an integrated circuit device, the method comprising:
generating a frequency-multiplied clock signal in response to an input clock signal;
determining a multiplication factor between respective frequencies of the input clock signal and the frequency-multiplied clock signal; and
selecting one of a plurality of frequency-divided clock signals to be an output clock signal based, at least in part, on a difference between the multiplication factor and a predetermined multiplier value.

2. The method of claim 1 further comprising generating the plurality of frequency-divided clock signals in response to the frequency-multiplied clock signal.

3. The method of claim 1 wherein determining the multiplication factor between respective frequencies of the input clock signal and the frequency-multiplied clock signal comprises counting transitions of the frequency-multiplied clock signal over an interval defined by transitions of the input clock signal.

4. The method of claim 1 wherein the predetermined multiplier value indicates a desired frequency ratio between the input clock signal and the output clock signal, the method further comprising determining a difference between the multiplication factor and the predetermined multiplier value.

5. The method of claim 4 further comprising receiving the predetermined multiplier value from a source external to the integrated circuit device and storing the predetermined multiplier value within a programmable register of the integrated circuit device, the programmable storage register being coupled to provide the predetermined multiplier value to the ratio logic.

6. The method of claim 4 wherein determining the difference between the multiplication factor and the predetermined multiplier value comprises dividing the multiplication factor by the predetermined multiplier value.

7. The method of claim 4 wherein determining the difference between the multiplication factor and the predetermined multiplier value comprises indexing a lookup table to obtain a value indicative of the difference between the multiplication factor and the predetermined multiplier value from the lookup table.

8. The method of claim 1 wherein generating the frequency-multiplied clock signal comprises generating a frequency-multiplied clock signal having a fixed frequency as the input clock signal frequency transitions between a plurality of different frequencies.

9. The method of claim 1 wherein generating the frequency-multiplied clock signal comprises generating a frequency-multiplied clock signal that transitions between different frequencies in response to transitions of the input clock signal frequency.

10. An integrated circuit device comprising:
a clock multiplier circuit to generate a frequency-multiplied clock signal in response to an input clock signal;
ratio logic to determine a multiplication factor between the frequencies of the input clock signal and the frequency-multiplied clock signal; and
clock selection circuitry to select one of a plurality of frequency-divided clock signals to be an output clock signal based, at least in part, on a difference between the multiplication factor and a predetermined multiplier value.

11. The integrated circuit device of claim 10 further comprising a clock divider circuit to generate the plurality of frequency-divided clock signals in response to the frequency-multiplied clock signal.

12. The integrated circuit device of claim 10 wherein the ratio logic to determine the multiplication factor between the frequencies of the input clock signal and the frequency-multiplied clock signal comprises circuitry to count transitions of the frequency-multiplied clock signal over an interval defined by transitions of the input clock signal.

13. The integrated circuit device of claim 10 wherein the predetermined multiplier value indicates a desired frequency ratio between the input clock signal and the output clock signal, and wherein the ratio logic comprises circuitry to determine the difference between the multiplication factor and the predetermined multiplier value.

14. The integrated circuit device of claim 13 further comprising a programmable storage register to store the predetermined multiplier value, the programmable storage register being coupled to provide the predetermined multiplier value to the ratio logic.

15. The integrated circuit device of claim 13 wherein the circuitry to determine the difference between the multiplication factor and the predetermined multiplier value comprises circuitry to divide the multiplication factor by the predetermined multiplier value.

16. The integrated circuit device of claim 13 wherein the circuitry to determine the difference between the multiplication factor and the predetermined multiplier value comprises a lookup table and circuitry to obtain a value indicative of the difference between the multiplication factor and the predetermined multiplier value from the lookup table.

17. The integrated circuit device of claim 10 further comprising:
a signaling interface to receive the predetermined multiplier value and an instruction to store the predetermined multiplier value from a source external to the integrated circuit device;
a programmable storage register; and
control circuitry to store the predetermined multiplier value within the programmable storage register in response to the instruction.

18. The integrated circuit device of claim 10 wherein the clock multiplier circuit to generate the frequency-multiplied clock signal comprises circuitry to generate a frequency-multiplied clock signal having a fixed frequency as the input clock signal frequency transitions between a plurality of different frequencies.

19. The integrated circuit device of claim 10 wherein the clock multiplier circuit to generate the frequency-multiplied clock signal comprises circuitry to generate a frequency-multiplied clock signal that transitions between different frequencies in response to transitions of the input clock signal frequency.

20. An apparatus comprising:
means for generating a frequency-multiplied clock signal in response to an input clock signal;
means for determining a multiplication factor between respective frequencies of the input clock signal and the frequency-multiplied clock signal; and
means for selecting one of a plurality of frequency-divided clock signals to be an output clock signal based, at least in part, on a difference between the multiplication factor and a predetermined multiplier value.

Assignees

• Rambus Inc

Inventors

• Zerbe Jared L
• Leibowitz Brian S
• Hossain Masum

Classifications

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03K5/13

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H03K5/00006

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H03J2200/10

  Tuning of a resonator by means of digitally controlled capacitor bank · CPC title

• H03K5/14

  by the use of delay lines (H03K5/133 takes precedence) · CPC title