Pulse driven power FET

Patent metadata

Field	Value
Publication number	US-10205447-B1
Application number	US-201816048146-A
Country	US
Kind code	B1
Filing date	Jul 27, 2018
Priority date	May 25, 2017
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

A power drive circuit is disclosed. The power circuit includes: a pulse detector, configured to generate first and second control signals in response to first and second pulse signals, respectively. The power drive circuit also includes a state storage device, configured to generate first and second driver input signals in response to the first and second control signals, respectively. The power drive circuit also includes a driver configured to generate first and second gate drive signals in response to the first and second driver input signals, respectively. The power drive circuit also includes a power switch, configured to receive the first and second gate drive signals, where the first and second gate drive signals control the power switch to selectively conduct or not conduct current between first and second terminals.

First claim

What is claimed is:

1. A power drive circuit, comprising:
a transformer, configured to generate first and second pulse signals;
a pulse detector, configured to receive the first and second pulse signals and to generate first and second control signals in response to the first and second pulse signals, respectively;
a state storage device, configured to receive the first and second control signals and to generate first and second driver input signals in response to the first and second control signals, respectively, wherein the state storage device is configured to generate the first driver input signal in response to the first control signal and to maintain the first driver input signal until receiving the second control signal despite no longer receiving the first control signal, wherein the state storage device is configured to generate the second driver input signal in response to the second control signal and to maintain the second driver input signal until receiving the first control signal despite no longer receiving the second control signal;
a driver configured to receive the first and second driver input signals and to generate first and second gate drive signals in response to the first and second driver input signals, respectively; and
a power switch, configured to receive the first and second gate drive signals, wherein the first and second gate drive signals control the power switch to selectively conduct or not conduct current between first and second terminals, wherein the first gate drive signal causes the power switch to conduct and the second gate drive signal causes the power switch to not conduct,
wherein the first control signal having a low logic state causes the state storage device to generate the first driver input signal.

2. The power drive circuit of claim 1 , wherein the transformer is configured to respectively generate the first and second pulses in response to rising and falling edges of a transformer input signal applied to the primary side of the transformer.

3. The power drive circuit of claim 1 , wherein a primary inductor of the transformer is configured to receive a pulse width modulation (PWM) signal, and a secondary inductor of the transformer is configured to generate the first and second pulse signals in response to the PWM signal.

4. The power drive circuit of claim 3 , wherein in response to a rising edge at the primary inductor, the secondary inductor generates a negative going pulse which causes the power switch to be conductive.

5. The power drive circuit of claim 1 , wherein the state storage device comprises a capacitor.

6. The power drive circuit of claim 1 , wherein the state storage device comprises a latch.

7. The power drive circuit of claim 1 , further comprising an overcurrent protection circuit, configured to cause the power switch to be nonconductive in response to an overcurrent condition.

8. The power drive circuit of claim 7 , wherein the overcurrent protection circuit is configured to sense the overcurrent condition by comparing a voltage based on a voltage difference between the first and second terminals with a threshold voltage.

9. The power drive circuit of claim 1 , wherein the pulse detector, the state storage device, the driver, and the power switch are integrated on a single GaN die.

10. A power circuit, comprising:
first and second power drive circuits, each configured to receive a plurality of pulse signals from a pulse generator, wherein each of the first and second power drive circuits comprises:
a transformer, configured to generate first and second pulse signals;
a pulse detector, configured to receive first and second pulse signals and to generate first and second control signals in response to the first and second pulse signals, respectively,
a state storage device, configured to receive the first and second control signals and to generate first and second driver input signals in response to the first and second control signals, respectively, wherein the state storage device is configured to generate the first driver input signal in response to the first control signal and to maintain the first driver input signal until receiving the second control signal despite no longer receiving the first control signal, wherein the state storage device is configured to generate the second driver input signal in response to the second control signal and to maintain the second driver input signal until receiving the first control signal despite no longer receiving the second control signal,
a driver configured to receive the first and second driver input signals and to generate first and second gate drive signals in response to the first and second driver input signals, respectively, and
a power switch, configured to receive the first and second gate drive signals, wherein the first and second gate drive signals control the power switch to selectively conduct or not conduct current between first and second terminals, wherein the first gate drive signal causes the power switch to conduct and the second gate drive signal causes the power switch to not conduct,
wherein the first control signal having a low logic state causes the state storage device to generate the first driver input signal.

11. The power circuit of claim 10 , wherein the transformer is configured to respectively generate the first and second pulses in response to rising and falling edges of a transformer input signal applied to the primary side of the transformer.

12. The power circuit of claim 10 , wherein a primary inductor of the transformer is configured to receive a pulse width modulation (PWM) signal, and the secondary inductor of the transformer is configured to generate the first and second pulse signals in response to the PWM signal.

13. The power circuit of claim 12 , wherein in response to a rising edge at the primary inductor, the secondary inductor generates a negative going pulse which causes the power switch of each power drive circuit to be conductive.

14. The power circuit of claim 10 , wherein the state storage device of each power drive circuit comprises a capacitor.

15. The power circuit of claim 10 , wherein the state storage device of each power drive circuit comprises a latch.

16. The power circuit of claim 10 , wherein each power drive circuit further comprises an overcurrent protection circuit, configured to cause the power switch to be nonconductive in response to an overcurrent condition.

17. The power circuit of claim 16 , wherein the overcurrent protection circuit of each power drive circuit is configured to sense the overcurrent condition by comparing a voltage based on a voltage difference between the first and second terminals with a threshold voltage.

18. The power circuit of claim 10 , wherein the pulse detector, the state storage device, the driver, and the power switch circuit of each power drive circuit are integrated on a single GaN die.

Assignees

• Navitas Semiconductor Inc

Inventors

• Ribarich Thomas
• Zhang Ju

Classifications

• H03K17/6235

  with storage of control signal · CPC title

• H03K17/691

  using transformer coupling · CPC title

• H03K2217/0027

  Measuring means of, e.g. currents through or voltages across the switch · CPC title

• H03K9/08

  of duration- or width-mudulated pulses {or of duty-cycle modulated pulses} · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title