Semiconductor device having a fin at a side of a semiconductor body

US10205019B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10205019-B2
Application numberUS-201615163428-A
CountryUS
Kind codeB2
Filing dateMay 24, 2016
Priority dateDec 3, 2012
Publication dateFeb 12, 2019
Grant dateFeb 12, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part of the fin, a drain extension region of a first conductivity type, a source region and a drain region of the first conductivity type, a source contact in contact with the source region, and a gate structure adjoining opposing walls of the fin. The source contact extends along a vertical direction along the source region. The source contact includes a conductive material and is disposed in a trench in the semiconductor body, adjacent to the source region. The body region and the drain extension region are arranged one after another between the source region and the drain region.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a fin at a first side of a semiconductor body; a body region of a second conductivity type in at least a part of the fin; a drain extension region of a first conductivity type; a source region and a drain region of the first conductivity type; a deep body region of the second conductivity type below the source region and electrically connected to the body region; a source contact in contact with the source region, the source contact comprising a conductive material and being disposed in a contact trench in the semiconductor body, adjacent to the source region, the source region extending in a vertical direction along the source contact; and a gate structure adjoining opposing walls of the fin, wherein the body region and the drain extension region are arranged one after another between the source region and the drain region, wherein the source contact is electrically connected to the deep body region. 2. The semiconductor device of claim 1 , wherein the source contact vertically extends to a bottom side of the source region. 3. The semiconductor device of claim 1 , wherein the fin includes at least part of the drain extension region. 4. The semiconductor device of claim 1 , further comprising a shallow trench isolation at a top face of the fin adjoining the drain extension region. 5. The semiconductor device of claim 1 , wherein the gate structure adjoins a top face of the fin. 6. The semiconductor device of claim 1 , further comprising a drain contact in contact with the drain region, the drain contact extending along a vertical direction along the drain region. 7. An integrated circuit comprising the semiconductor device of claim 1 . 8. A semiconductor device comprising: a fin at a first side of a semiconductor body; a body region of a second conductivity type in at least a part of the fin; a drain extension region of a first conductivity type; a source region and a drain region of the first conductivity type; a deep body region of the second conductivity type below the source region and electrically connected to the body region; a drain contact in contact with the drain region, the drain contact comprising a conductive material and being disposed in a contact trench in the semiconductor body, adjacent to the drain region, the drain region extending in a vertical direction along the drain contact to a bottom side of the contact trench; a gate structure adjoining opposing walls of the fin; and a doped layer beneath the drain region, wherein the body region and the drain extension region are arranged one after another between the source region and the drain region, and the drain contact is electrically connected to the doped layer via a first contact layer, and wherein the source contact is electrically connected to the deep body region. 9. The semiconductor device of claim 8 , wherein the drain contact vertically extends to a bottom side of the drain region. 10. The semiconductor device of claim 8 , wherein the fin includes at least part of the drain extension region. 11. The semiconductor device of claim 8 , wherein the gate structure adjoins the top face of the fin. 12. An integrated circuit comprising the semiconductor device of claim 8 . 13. A method of manufacturing a semiconductor device, the method comprising: forming a fin at a first side of a semiconductor body; forming a body region of a second conductivity type in at least a part of the fin; forming a drain extension region of a first conductivity type; forming a source contact comprising forming a contact trench in the semiconductor body and filling a conductive material into the contact trench; forming a source region and a drain region of the first conductivity type; forming a gate structure adjoining opposing walls of the fin, wherein forming the source region comprises forming a material of a diffusion source at walls of the contact trench and diffusing dopants from the diffusion source into the semiconductor body, wherein the body region and the drain extension region are arranged one after another between the source region and the drain region. 14. The method of claim 13 , wherein the material of the diffusion source comprises a doped silicate glass.

Assignees

Inventors

Classifications

  • Diffusion sources · CPC title

  • within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US10205019B2 cover?
One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part of the fin, a drain extension region of a first conductivity type, a source region and a drain region of the first conductivity type, a source contact in contact with the source region, and a gate structure adjoining opposing walls of th…
Who is the assignee on this patent?
Infineon Technologies Austria Ag
What technology area does this patent fall under?
Primary CPC classification H01L29/7833. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 12 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).