Bottom source NMOS triggered Zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)

US10205017B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10205017-B2
Application numberUS-201314037205-A
CountryUS
Kind codeB2
Filing dateSep 25, 2013
Priority dateJun 17, 2009
Publication dateFeb 12, 2019
Grant dateFeb 12, 2019

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.

First claim

Opening claim text (preview).

I claim: 1. A method of forming a transient voltage suppressing (TVS) device comprising: forming an epitaxial layer of a first conductivity type on top of a semiconductor substrate wherein the semiconductor substrate comprises a heavily doped bottom layer of the first conductivity type; forming a trench gate padded with a gate insulation layer and filled with a gate material in the trench gate in the epitaxial layer; forming a body region with a second conductivity type in the epitaxial layer next to the trench gate and forming a drain contact region and an epitaxial contact region of the first conductivity type with the drain contact region encompassed in the body region and the epitaxial contact region disposed in the epitaxial layer, forming a body contact region of the second conductivity type near a top surface of the body region disposed at a distance from the drain contact region; and forming a bottom source/emitter/anode electrode layer beneath the semiconductor substrate and forming on a top surface of the epitaxial layer a drain/collector/cathode electrode to contact the trench gate and the drain contact region and further forming a body to source short to electrically short the body contact region to the epitaxial contact region thus forming a TVS structure comprises a TVS diode, a vertical bipolar transistor and a bottom-source metal-oxide-semiconductor field effect transistor (BS-MOSFET) as three parallel connected vertical circuits between the drain/collector/cathode electrode disposed on top of the epitaxial layer and the bottom source/emitter/anode electrode layer. 2. The method of claim 1 wherein: the forming the drain/collector/cathode electrode to contact the trench gate and the drain region is a step of making the trench gate and the drain/collector/cathode electrode to have a same potential. 3. The method of claim 1 wherein: the forming the trench gate further comprising a step of forming the trench gate with a predesignated width according to a ratio of an area occupied by the drain contact region to an area occupied by the BS-MOSFET. 4. The method of claim 3 wherein: the forming the trench gate further comprising a step of forming the trench gate with a predesignated width according to a current flow through the BS-MOSFET required to trigger the vertical bipolar transistor. 5. The method of claim 1 wherein: the forming the epitaxial layer further comprising forming the epitaxial layer to have a predesignated resistance for adjusting a current flow through the BS-MOSFET to trigger the vertical bipolar transistor.

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10205017B2 cover?
A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the b…
Who is the assignee on this patent?
Bobde Madhur, Alpha & Omega Semiconductor
What technology area does this patent fall under?
Primary CPC classification H01L29/7827. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 12 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).