Method for manufacturing an integrated circuit including a lateral trench transistor and a logic circuit element

Patent metadata

Field	Value
Publication number	US-10205016-B2
Application number	US-201715484206-A
Country	US
Kind code	B2
Filing date	Apr 11, 2017
Priority date	Apr 13, 2016
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.

First claim

What is claimed is:

1. A method of forming an integrated circuit including a lateral trench transistor and a logic circuit element, the method comprising:
forming a plurality of gate trenches in a first main surface of a semiconductor substrate, wherein a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface;
forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches;
forming a source region comprising performing a doping process by introducing dopants through a sidewall of the source contact groove;
filling a sacrificial material in the source contact groove;
forming components of the logic circuit element after filling the sacrificial material in the source contact groove;
removing the sacrificial material from the source contact groove after forming the components of the logic circuit element; and
filling a source conductive material in the source contact groove.

2. The method of claim 1 , wherein forming components of the logic circuit comprises forming components of a transistor.

3. The method of claim 2 , wherein forming components of the transistor comprises forming a source and a drain region.

4. The method of claim 1 , further comprising forming gate contacts each contacting a conductive material in a corresponding one of the gate trenches.

5. The method of claim 4 , wherein the gate contacts, contacts to the source conductive material and contact plugs to components of the logic circuit are formed by joint processes.

6. The method of claim 1 , further comprising forming field plate trenches, wherein the field plate trenches, the gate trenches and the source contact groove are formed by joint etching processes.

7. The method of claim 6 , further comprising forming a field oxide layer to line the field plate trenches, wherein the field oxide layer fills the gate trenches and the source contact groove.

8. The method of claim 1 , further comprising forming field plate trenches before forming the gate trenches.

9. The method of claim 8 , further comprising forming a field oxide layer before forming the gate trenches.

10. The method of claim 1 , further comprising forming a first doped portion of a first conductivity type in a region of the semiconductor substrate before forming the plurality of gate trenches, wherein the gate trenches and the source contact groove are formed in the first doped portion.

11. A method of forming an integrated circuit including a lateral trench transistor and a logic circuit element, the method comprising:
forming a plurality of gate trenches in a first main surface of a semiconductor substrate, wherein a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface;
forming a drain contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the drain contact groove extending along the plurality of gate trenches;
forming a drain region comprising performing a doping process by introducing dopants of a first conductivity type through a sidewall of the drain contact groove;
filling a sacrificial material in the drain contact groove;
forming components of the logic circuit element after filling the sacrificial material in the drain contact groove;
removing the sacrificial material from the drain contact groove after forming the components of the logic circuit element; and
filling a conductive material in the drain contact groove.

12. The method of claim 11 , further comprising forming a second doped portion of a second conductivity type in a region of the semiconductor substrate, wherein the gate trenches and the drain contact groove are formed in the second doped portion of the second conductivity type.

13. A semiconductor device comprising an array of transistor cells, each of the transistor cells formed in a semiconductor substrate having a first main surface and comprising:
a body region disposed between a source region and a drain region in the semiconductor substrate;
gate trenches extending from the first main surface into the body region, a longitudinal axis of the gate trenches running in a first direction parallel to the first main surface, the source region, the body region, and the drain region being arranged along the first direction;
a source contact groove formed in the semiconductor substrate and running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the gate trenches and being filled with a conductive material to form a source contact arranged in the source contact groove, the source region being arranged adjacent to the source contact groove;
gate electrodes arranged in the gate trenches; and
gate contacts, each for connecting one of the gate electrodes to a gate terminal, the gate contacts being spatially separate from each other,
wherein the source contact arranged in the source contact groove is separated from the body region by the source region.

14. The semiconductor device of claim 13 , wherein the source region and the drain region are of a first conductivity type, wherein the semiconductor substrate further comprises a second doped portion of a second conductivity type, and wherein the source contact groove is arranged in the second doped portion of the second conductivity type.

15. An integrated circuit comprising the semiconductor device of claim 13 and a logic circuit element formed in the semiconductor substrate.

16. The semiconductor device of claim 13 , further comprising a drain contact groove formed in the semiconductor substrate and running in the second direction parallel to the first main surface, the drain contact groove being filled with a conductive material to form a drain contact arranged in the drain contact groove, the drain region being arranged adjacent to the drain contact groove.

17. The semiconductor device of claim 13 , further comprising a body contact portion disposed beneath the source contact groove and electrically connecting the body region with the source contact.

18. The semiconductor device of claim 17 , wherein the body contact portion is disposed at a sidewall of the source contact groove.

19. The semiconductor device of claim 17 , wherein the body contact portion extends under the gate trenches.

20. The semiconductor device of claim 17 , further comprising a drift zone disposed between the body region and the drain region along the first direction, wherein the body contact portion extends to the drift zone.

Assignees

• Infineon Technologies Ag

Inventors

• Meiser Andreas
• Schloesser Till
• Weber Detlef
• Gebhardt Karl-Heinz

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H01L29/1095

  Electricity · mapped topic

• H01L27/0623

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic

• H01L29/41766

  Electricity · mapped topic