Systems, processes and computer-accessible medium for providing a bi-directional scan path for peak capture power reduction in launch-off-shift testing

Patent metadata

Field	Value
Publication number	US-10203368-B2
Application number	US-201313735679-A
Country	US
Kind code	B2
Filing date	Jan 7, 2013
Priority date	Jan 6, 2012
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

Exemplary systems, methods and computer-readable mediums can assign, from the circuit, at least two scan cells as at least two interface registers, and generate at least one bidirectional scan path between the at least two interface registers of the at least one portion of the circuit. The at least two interface registers can be disposed in neighboring positions, and the assigning can include a partitioning procedure that can iteratively merge the scan cells of the at least one portion of the circuit into a plurality of regions.

First claim

What is claimed is:

1. A non-transitory computer-readable medium having stored thereon computer-executable instructions for modifying or generating at least one portion of a circuit, wherein, when a computer hardware arrangement executes the instructions, the computer arrangement is configured to perform procedures comprising:
assigning, from the circuit, at least two scan cells as at least two interface registers, wherein the assigning includes a partitioning procedure which includes iteratively merging the scan cells of the at least one portion of the circuit into a plurality of regions; and
generating at least one bidirectional scan path between the at least two interface registers of the at least one portion of the circuit, wherein the at least one bidirectional scan path includes a plurality of scan paths between two of the at least two interface registers of the plurality of regions which are bidirectional.

2. The computer-readable medium of claim 1 , wherein the at least two interface registers are disposed in neighboring positions on at least one scan chain.

3. The computer-readable medium of claim 1 , wherein the iterative merging procedure maintains an acyclicity of the regions.

4. The computer-readable medium of claim 1 , wherein the iterative procedure merging includes optimizing a power consumption and area cost of the at least one portion of the circuit.

5. The computer-readable medium of claim 1 , wherein the at least two interface registers are minimized using a custom heuristic.

6. The computer-readable medium of claim 1 , wherein the at least one bidirectional scan path connects the at least two scan cells to one another in a bi-directional manner.

7. The computer-readable medium of claim 1 , wherein the at least two scan cells include internal scan cells.

8. A circuit, comprising:
a first interface register of scan cells;
a second interface register of scan cells, which neighbors the first interface register; and
a bidirectional scan path between the first and second interface registers, wherein the bidirectional scan path includes a plurality of scan paths between two further interface registers of a plurality of regions which are bidirectional;
wherein the first and second interface registers are assigned using a partitioning procedure which includes iteratively merging the scan cells of the at least one portion of the circuit into the plurality of regions.

9. The circuit of claim 8 , wherein the at least two interface registers are disposed in neighboring positions on at least one scan chain.

10. The circuit of claim 8 , wherein the iterative merging procedure maintains an acyclicity of the regions.

11. The circuit of claim 8 , wherein the iterative merging procedure includes optimizing a power consumption and area cost of at least one portion of the circuit.

12. The circuit of claim 8 wherein the first and second interface registers are minimized using a custom heuristic.

13. The circuit of claim 8 , wherein the at least one bidirectional scan path connects the scan cells to one another in a bi-directional manner.

14. The circuit of claim 8 , wherein the scan cells include internal scan cells.

Assignees

• Univ New York

Inventors

• Sinanoglu Ozgur

Classifications

• G01R31/318558

  Addressing or selecting of subparts of the device under test · CPC title

• G01R31/28 Primary

  Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits G01R31/002;} testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers {or computer components} G06F11/00; checking static stores for correct operation G11C29/00 {; testing receivers or transmitters of transmission systems H04B17/00}) · CPC title

• G01R31/318575 Primary

  Power distribution; Power saving · CPC title