Recording element substrate, liquid discharge head, and recording apparatus

Patent metadata

Field	Value
Publication number	US-10201969-B2
Application number	US-201815901619-A
Country	US
Kind code	B2
Filing date	Feb 21, 2018
Priority date	Feb 22, 2017
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

A recording element substrate includes a signal supply circuit and a common line which connects the signal supply circuit to first logic circuit array for a recording element and a second logic circuit array for a memory element in common. Furthermore, the first and second logic circuit arrays extend along a direction in which the common line extends, the first logic circuit array is disposed on one side of the common line, the second logic circuit array is disposed on the other side of the common line, and the first and second logic circuit arrays are arranged so that at least a portion of the first logic circuit array and a portion of the second logic circuit array overlap with each other in a direction orthogonal to the extending direction.

First claim

What is claimed is:

1. A recording element substrate comprising:
a plurality of recording elements;
a first logic circuit array which is an array of first logic circuits which correspond to the recording elements;
a plurality of memory elements;
a second logic circuit array which is an array of second logic circuits which correspond to the plurality of memory elements;
a signal supply circuit configured to supply a signal for controlling the plurality of recording elements and a signal for controlling the plurality of memory elements; and
a common line configured to connect the signal supply circuit to the first logic circuit array and the second logic circuit array in common,
wherein the first and second logic circuit arrays extend along a direction in which the common line extends, the first logic circuit array is disposed on one side of the common line, the second logic circuit array is disposed on the other side of the common line, and the first and second logic circuit arrays are arranged so that at least a portion of the first logic circuit array and a portion of the second logic circuit array overlap with each other in a direction orthogonal to the extending direction.

2. The recording element substrate according to claim 1 , wherein portions of the first logic circuits and portions of the second logic circuits overlap with each other in a direction orthogonal to the extending direction.

3. The recording element substrate according to claim 1 , wherein each of the first logic circuits and the common line are connected to each other through a first discrete wiring which extends along a direction which intersects with the extending direction, and each of the second logic circuits and the common line are connected to each other through a second discrete wiring which extends along the intersecting direction.

4. The recording element substrate according to claim 1 , wherein a connection portion of the first discrete wiring and the common line is the same as a connection portion of the second discrete wiring and the common line.

5. The recording element substrate according to claim 1 , wherein the common line includes a line which supplies a signal for switching driving such that the plurality of recording elements or the plurality of memory elements are driven.

6. The recording element substrate according to claim 1 , wherein the plurality of recording elements and the plurality of memory elements are exclusively driven in accordance with a signal supplied from the signal supply circuit.

7. The recording element substrate according to claim 1 , wherein a pitch between adjacent first logic circuits is equal to a pitch between adjacent second logic circuits.

8. The recording element substrate according to claim 7 , wherein a pitch between the first logic circuits in the first logic circuit array is equal to a pitch between the second logic circuits in the second logic circuit array.

9. The recording element substrate according to claim 1 , wherein a pitch between the second logic circuits in the second logic circuit array is an integral multiple of a pitch between the first logic circuits in the first logic circuit array.

10. The recording element substrate according to claim 1 , further comprising:
first driving elements connected to the recording elements and the first logic circuits;
second driving elements connected to the memory elements and the second logic circuits; and
a ground line connected to the first and second driving elements in common.

11. The recording element substrate according to claim 1 , wherein the signal supply circuit is disposed in an edge portion of the recording element substrate in the extending direction.

12. The recording element substrate according to claim 1 , wherein the plurality of memory elements are anti-fuse elements.

13. The recording element substrate according to claim 1 , comprising:
a recording element array which is an array of the plurality of recording elements; and
a memory element array which is an array of the plurality of memory elements.

14. The recording element substrate according to claim 13 , wherein the number of recording elements included in the recording element array is equal to or larger than the number of memory elements included in the memory element array.

15. The recording element substrate according to claim 13 , wherein the number of memory element arrays is smaller than the number of recording element arrays.

16. The recording element substrate according to claim 13 , wherein the recording element array and the memory element array extend in the extending direction, the recording element array is disposed on a side opposite to a side in which the common line is disposed relative to the first logic circuit array, and the memory element array is disposed a side opposite to a side in which the common line is disposed relative to the second logic circuit array.

17. A liquid discharge head comprising:
a recording element substrate including
a plurality of recording elements,
a first logic circuit array which is an array of first logic circuits which correspond to the recording elements,
a plurality of memory elements,
a second logic circuit array which is an array of second logic circuits which correspond to the plurality of memory elements,
a signal supply circuit configured to supply a signal for controlling the plurality of recording elements and a signal for controlling the plurality of memory elements, and
a common line configured to connect the signal supply circuit to the first logic circuit array and the second logic circuit array in common, and

a discharge port member including discharge ports corresponding to the plurality of recording elements,
wherein the first and second logic circuit arrays extend along a direction in which the common line extends, the first logic circuit array is disposed on one side of the common line, the second logic circuit array is disposed on the other side of the common line, and the first and second logic circuit arrays are arranged so that at least a portion of the first logic circuit array and a portion of the second logic circuit array overlap with each other in a direction orthogonal to the extending direction.

18. The liquid discharge head according to claim 17 , wherein a portion of the first logic circuit and a portion of the second logic circuit overlap with each other in a direction orthogonal to the extending direction.

19. The liquid discharge head according to claim 17 , wherein each of the first logic circuits and the common line are connected to each other through a first discrete wiring which extends along a direction which intersects with the extending direction, and each of the second logic circuits and the common line are connected to each other through a second discrete wiring which extends in the intersecting direction.

20. A recording apparatus which performs recording using a liquid discharge head comprising:
a recording element substrate including
a plurality of recording elements,
a first logic circuit array which is an array of first logic circuits which correspond to the plurality of recording elements,
a plurality of memory elements,
a second logic circuit array which is an array of second logic circuits which correspond to the plurality of memory elements,
a signal supply circuit configured to supply a signal for controlling the plurality of recording elements and a signal for controlling the plurality of memory elements, and
a common line configured to conn

Assignees

• Canon Kk

Inventors

• Negishi Toshio
• Taniguchi Suguru
• Fujii Kazunari

Classifications

• B41J2/04541 Primary

  Specific driving circuit · CPC title

• B41J2/0455

  Details of switching sections of circuit, e.g. transistors · CPC title

• B41J2/04523

  reducing size of the apparatus · CPC title

• B41J2/17546

  electronically · CPC title

• H10B20/25

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title