Clock synchronization method, device, and system
US-2024421929-A1 · Dec 19, 2024 · US
US10200962B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10200962-B2 |
| Application number | US-201816103376-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 14, 2018 |
| Priority date | Jun 16, 2015 |
| Publication date | Feb 5, 2019 |
| Grant date | Feb 5, 2019 |
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An audio device includes a signal input interface, a first output interface, a second output interface, at least one processing circuit configured as a buffer control portion, at least one memory configured to store an audio signal. The buffer control portion sets a second reading position at a position that precedes a first reading position of the first output interface by delay time, and, when starting output of the audio signal, writes silent data for the delay time in the memory and sets the first reading position at the head of the silent data.
Opening claim text (preview).
What is claimed is: 1. An audio device comprising: a signal input interface configured to input an audio signal; a first output interface; a second output interface; at least one processing circuit configured as a buffer control portion; and at least one memory configured to store the audio signal and instructions that, when executed by the at least one processing circuit, wherein: the buffer control portion sets a first reading position being a reading position of the audio signal stored in the memory with respect to the first output interface, and a second reading position being a reading position of the audio signal stored in the memory with respect to the second output interface and being a position that precedes the first reading position by delay time; and the buffer control portion, when starting output of the audio signal, writes silent data for the delay time in the memory with respect to the first output interface and sets the first reading position at a head of the silent data. 2. The audio device according to claim 1 , wherein the memory includes: a first memory; and a second memory; the at least one processing circuit is further configured to: write the audio signal in the first memory and the second memory; and read the audio signal from the memory; the first reading position is set in the first memory; and the second reading position is set in the second memory. 3. The audio device according to claim 2 , wherein the at least one processing circuit is further configured to discard the audio signal before the second reading position in the second memory. 4. An audio system comprising: the audio device according to claim 1 ; a first reproducing device configured to reproduce the audio signal that is output from the first output interface; and a second reproducing device configured to reproduce the audio signal that is output from the second output interface, wherein the delay time corresponds to a time lag between input of the audio signal to the first reproducing device and input of the audio signal to the second reproducing device. 5. The audio system according to claim 4 , wherein a transmission system from the first output interface to the first reproducing device and a transmission system from the second output interface to the second reproducing device have different transmission rates. 6. A synchronous reproduction method comprising: inputting an audio signal; storing an input audio signal; and when starting output by reading a temporarily stored audio signal from a first reading position and a second reading position, writing silent data for delay time in front of the temporarily stored audio signal, setting the first reading position at the head of the silent data, and setting the second reading position at a position that precedes the first reading position by the delay time. 7. The synchronous reproduction method according to claim 6 , further comprising: reading the audio signal from a first memory; reading the audio signal from a second memory; writing the audio signal in the first memory; writing the audio signal in the second memory; setting the first reading position in the first memory; and setting the second reading position in the second memory. 8. The synchronous reproduction method according to claim 7 , further comprising discarding the audio signal before the second reading position in the second memory.
one node acting as a reference for the others · CPC title
Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F) · CPC title
Arrangements for synchronising broadcast or distribution via plural systems · CPC title
for local area · CPC title
to plural spots in a confined site, e.g. MATV [Master Antenna Television] · CPC title
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