Analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10200052-B2
Application number	US-201715859437-A
Country	US
Kind code	B2
Filing date	Dec 30, 2017
Priority date	Jul 6, 2017
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

In some examples, a system comprises an analog-to-digital converter (ADC) to receive an analog input signal and a reset signal, the ADC to convert the analog input signal into a digital signal. The system comprises a digital-to-analog converter (DAC), coupled to the ADC, to convert the digital signal into an internal analog signal. The system includes a first capacitor, coupled to the DAC, to receive the internal analog signal. The system comprises a first switch, coupled to the first capacitor, to provide the analog input signal to the first capacitor. The system comprises a second switch to couple the first capacitor to ground.

First claim

What is claimed is:

1. A system comprising:
an analog-to-digital converter (ADC) to receive an analog input signal and a reset signal, the ADC to convert the analog input signal into a digital signal;
a digital-to-analog converter (DAC), coupled to the ADC, to convert the digital signal into an internal analog signal;
a buffer;
a first capacitor, coupled to an output of the buffer, and an output of the DAC;
a first switch, coupled between the buffer output and the first capacitor; and
a second switch to couple the first capacitor to ground;
a second capacitor coupled between an input to the buffer and ground; and
a third switch, coupled to the buffer, the second capacitor, and the ADC, to provide the analog input signal to the buffer, the second capacitor, and the ADC while the reset signal is in an asserted state,
the first switch to provide the analog input signal to the first capacitor while the second switch is in a closed state, and the reset signal is in a deasserted state, and
the DAC to provide the internal analog signal to the first capacitor while the first switch is in an open state and the second switch is in an open state.

2. The system of claim 1 , wherein the first and second switches are both controlled by a switch signal.

3. The system of claim 2 , wherein the first capacitor is to output a modified analog signal based on the received internal analog signal and the analog input signal.

4. The system of claim 3 , wherein the modified analog signal indicates a difference in voltage values of the received internal analog signal and the analog input signal.

5. The system of claim 3 , further comprising:
an amplifier, coupled to the first capacitor, to amplify the modified analog signal.

6. The system of claim 1 , wherein the third switch is in a closed state while the DAC provides the internal analog signal to the first capacitor, the first switch is in an open state, and the second switch is in an open state.

7. The system of claim 6 , further comprising:
an amplifier, coupled to the first capacitor, to receive a modified analog signal, wherein the first capacitor is to output the modified analog signal based on the received internal analog signal and the analog input signal.

8. The system of claim 7 , wherein the amplifier is part of a first stage and further comprising a second stage coupled to the first stage, wherein an output of the amplifier is an analog input signal to the second stage.

9. The system of claim 8 further comprising:
a time alignment unit to receive a digital signal of the first stage and a digital signal of the second stage and to combine the digital signal of the first stage with the digital signal of the second stage to indicate a voltage level of an analog input signal to the first stage.

10. The system of claim 1 , further comprising:
a second buffer, coupled to the third switch, to provide the analog input signal to the third switch;
a third buffer, coupled to the ADC, to provide the analog input signal to the ADC;
a third capacitor coupled to ground; and
a fourth switch, coupled to the second buffer, the third buffer, and the third capacitor, to provide the analog input signal to the second buffer, the third buffer, and the third capacitor.

Assignees

• Texas Instruments Inc

Inventors

• Shrivastava Neeraj
• Kaviladath Jafar Sadique

Classifications

• H03M1/164 Primary

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title

• H03M1/146

  all stages being simultaneous converters · CPC title

• H03M1/001 Primary

  Analogue/digital/analogue conversion · CPC title