Phased array antenna panel having reduced passive loss of received signals

Patent metadata

Field	Value
Publication number	US-10199717-B2
Application number	US-201615356172-A
Country	US
Kind code	B2
Filing date	Nov 18, 2016
Priority date	Nov 18, 2016
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A phased array antenna panel includes a first plurality of antennas, a first radio frequency (RF) front end chip, a second plurality of antennas, a second RF front end chip, and a combiner RF chip. The first and second RF front end chips receive respective first and second input signals from the first and second pluralities of antennas, and produce respective first and second output signals based on the respective first and second input signals. The combiner RF chip can receive the first and second output signals and produce a power combined output signal that is a combination of powers of the first and second output signals. Alternatively, a power combiner can receive the first and second output signals and produce a power combined output signal, and the combiner RF chip can receive the power combined output signal.

First claim

The invention claimed is:

1. A phased array antenna panel, comprising:
a first radio frequency (RF) front end chip arranged between a first plurality of antennas,
wherein said first RF front end chip is configured to:
receive first input signals from said first plurality of antennas, and
produce a first output signal based on said first input signals;

a second RF front end chip arranged between a second plurality of antennas,
wherein said second RF front end chip is configured to:
receive second input signals from said second plurality of antennas, and
produce a second output signal based on said second input signals;

a master chip configured to:
provide, via said first RF front end chip, a first phase shift signal for said first plurality of antennas based on said received first input signals, and
provide, via said second RF front end chip, a second phase shift signal for said second plurality of antennas based on said received second input signals; and

a combiner RF chip configured to:
receive said first output signal and said second output signal, and
produce a power combined output signal that is a combination of a first power of said first output signal and a second power of said second output signal.

2. The phased array antenna panel of claim 1 , wherein said combiner RF chip comprises a lumped-element power combiner.

3. The phased array antenna panel of claim 2 , wherein said lumped-element power combiner comprises on-chip capacitors and inductors.

4. The phased array antenna panel of claim 1 , wherein said first output signal and said second output signal are fed into respective input buffers in said combiner RF chip.

5. The phased array antenna panel of claim 1 , wherein said combiner RF chip includes an output buffer, and
wherein the output buffer is configured to generate a buffered power combined output signal based on said power combined output signal.

6. The phased array antenna panel of claim 1 , wherein each antenna of said first plurality of antennas and said second plurality of antennas includes a vertically polarized probe and a horizontally polarized probe,
wherein corresponding vertically polarized probe and corresponding horizontally polarized probe of said first plurality of antennas are connected to said first RF front end chip via a plurality of first electrical connectors, and
wherein corresponding vertically polarized probe and corresponding horizontally polarized probe of said second plurality of antennas are connected to said second RF front end chip via a plurality of second electrical connectors.

7. The phased array antenna panel of claim 1 , wherein said combiner RF chip is substantially centered between said first RF front end chip and said second RF front end chip.

8. The phased array antenna panel of claim 1 , wherein said master chip is further configured to:
provide, via said first RF front end chip, a first amplitude control signal for said first plurality of antennas based on said received first input signals, and
provide, via said second RF front end chip, a second amplitude control signal for said second plurality of antennas based on said received second input signals.

9. The phased array antenna panel of claim 1 , wherein said first plurality of antennas comprises four antennas.

10. The phased array antenna panel of claim 9 , wherein said first input signals comprise four input signals from said four antennas.

11. A phased array antenna panel comprising:
a first radio frequency (RF) front end chip arranged between a first plurality of antennas,
wherein said first RF front end chip is configured to:
receive first input signals from said first plurality of antennas, and
produce a first output signal based on said first input signals;

a second RF front end chip arranged between a second plurality of antennas,
wherein said second RF front end chip is configured to:
receive second input signals from said second plurality of antennas, and
produce a second output signal based on said second input signals;

a master chip configured to:
provide, via said first RF front end chip, a first phase shift signal for said first plurality of antennas based on said received first input signals, and
provide, via said second RF front end chip, a second phase shift signal for said second plurality of antennas based on said received second input signals,

a power combiner on a substrate of said phased array antenna panel,
wherein said power combiner comprising microstrips that are configured to:
receive said first output signal and said second output signal, and
output a power combined output signal; and

a combiner RF chip configured to receive said power combined output signal.

12. The phased array antenna panel of claim 11 , wherein said combiner RF chip is configured to produce a buffered power combined output signal based on said power combined output signal.

13. The phased array antenna panel of claim 11 , wherein said power combined output signal is fed into an input buffer in said combiner RF chip.

14. The phased array antenna panel of claim 11 , wherein each antenna of said first plurality of antennas and said second plurality of antennas includes a vertically polarized probe and a horizontally polarized probe,
wherein corresponding vertically polarized probe and corresponding horizontally polarized probe of said first plurality of antennas are connected to said first RF front end chip via a plurality of first electrical connectors, and
wherein corresponding vertically polarized probe and corresponding horizontally polarized probe of said second plurality of antennas are connected to said second RF front end chip via a plurality of second electrical connectors.

15. The phased array antenna panel of claim 11 , wherein said combiner RF chip is substantially centered between said first RF front end chip and said second RF front end chip.

16. The phased array antenna panel of claim 11 , wherein said master chip is further configured to;
provide, via said first RF front end chip, a first amplitude control signal for said first plurality of antennas based on said received first input signals, and
provide, via said second RF front end chip, a second amplitude control signal for said second plurality of antennas based on said received second input signals.

17. The phased array antenna panel of claim 11 , wherein said first plurality of antennas comprises four antennas.

18. The phased array antenna panel of claim 17 , wherein said first input signals comprise four input signals from said four antennas.

Assignees

• Movandi Corp

Inventors

• Rofougaran Ahmadreza
• Yoon Seunghwan
• Besoli Alfred Grau
• Shirinfar Farid
• Gharavi Sam
• Boers Michael
• Rofougaran Maryam

Classifications

• H01Q1/523

  between antennas of an array · CPC title

• H01Q21/065

  Patch antenna array · CPC title

• H01Q25/001

  Crossed polarisation dual antennas (orthomode horns H01Q13/0258; cross-polarised rear feeds H01Q19/136; orthomode transducers H01P1/161) · CPC title

• H01Q1/2283 Primary

  mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package · CPC title

• H01Q3/26

  varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture ({H01Q3/12,} H01Q3/22, H01Q3/24 take precedence) · CPC title