Fabrication of optical metasurfaces

Patent metadata

Field	Value
Publication number	US-10199415-B2
Application number	US-201715799654-A
Country	US
Kind code	B2
Filing date	Oct 31, 2017
Priority date	Feb 22, 2017
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

The method is provided for fabricating an optical metasurface. The method may include depositing a conductive layer over a holographic region of a wafer and depositing a dielectric layer over the conducting layer. The method may also include patterning a hard mask on the dielectric layer. The method may further include etching the dielectric layer to form a plurality of dielectric pillars with a plurality of nano-scale gaps between the pillars.

First claim

What is claimed is:

1. A method for fabricating an optical metasurface, the method comprising:
depositing a conductive layer over a holographic region of a wafer;
depositing a dielectric layer over the conducting layer;
patterning a hard mask on the dielectric layer; and
etching the dielectric layer to form a plurality of dielectric pillars with a plurality of nano-scale gaps between the pillars.

2. The method of claim 1 , wherein the patterning is performed by e-beam lithography.

3. The method of claim 1 , wherein the patterning is performed by deep UV immersion lithography.

4. The method of claim 1 , further comprising filling the plurality of nano-scale gaps with a refractive index tunable core material.

5. The method of claim 4 , wherein the refractive index tunable core material comprises a liquid crystal or EO polymers.

6. The method of claim 5 , the step of filling the plurality of nano-scale gaps comprising:
preparing the surface to be hydrophobic or hydrophilic;
spin coating the liquid crystal over the plurality of pillars;
filling the liquid crystal into the nano-scale gap by a capillary action; and
encapsulating the liquid crystal with a clear coating.

7. The method of claim 5 , the step of filling the plurality of nano-scale gaps comprising:
applying a coating to a first portion of the plurality of nano-scale gaps;
spin coating the liquid crystal onto the plurality of dielectric pillars;
filling the liquid crystal into a second portion of the plurality of nano-scale gaps by a capillary action; and
encapsulating the liquid crystal with a clear coating.

8. The method of claim 1 , wherein the plurality of dielectric pillars comprises a constant gap between each of the pillars.

9. The method of claim 1 , wherein the plurality of dielectric pillars comprises a plurality of pairs of dielectric pillars.

10. The method of claim 9 , wherein the gap between each pair of pillars is smaller than the gap between two adjacent pairs of pillars.

11. The method of claim 1 , wherein the plurality of dielectric pillars comprises amorphous silicon.

12. The method of claim 1 , wherein the refractive index tunable core material comprises chalcogenide glass.

13. The method of claim 12 , the step of filling the plurality of nano-scale gaps comprising:
depositing the chalcogenide glass over the dielectric pillars by sputtering; and removing the chalcogenide glass from all areas except inside the plurality of nano-scale gaps.

14. The method of claim 1 , the step of depositing a dielectric layer over a conducting layer comprising:
depositing an etch-stop dielectric layer over the conducting layer; and
depositing the dielectric layer over the etch-stop dielectric layer.

15. The method of claim 14 , wherein the etch-stop dielectric layer comprises Al 2 O 3 .

16. The method of claim 1 , wherein the aspect ratio of height to width of the nano-scale gap is at least 5.

17. The method of claim 1 , the step of patterning a hard mask on the dielectric layer comprising:
depositing a hard mask over the dielectric layer;
patterning the hard mask to remove a first portion of the hard mask near an interconnect region;
patterning the hard mask by a high resolution process to form the nano-scale gap;
plasma etching the hard mask to remove a second portion of the hard mask in the nano-scale gap to expose the dielectric layer.

18. The method of claim 17 , wherein the hard mask comprises Al 2 O 3 .

19. The method of claim 17 , wherein patterning the hard mask to remove a first portion of the hard mask near an interconnect region is performed by a low resolution process.

20. The method of claim 1 , further comprising forming a plurality of conductive contacts over an interconnect region of the wafer for wire bonding to a CMOS, the plurality of conductive contacts configured to apply voltage to the plurality of dielectric pillars.

21. An optical metasurface fabricated by the method of claim 1 .

Assignees

• Elwha Llc

Inventors

• Akselrod Gleb M
• Josberger Erik E
• Weidman Mark C

Classifications

• H10W90/00

  Package configurations · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N23/54

  Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils · CPC title

• G02B5/1809

  with pitch less than or comparable to the wavelength · CPC title

• G01S7/4813

  Housing arrangements · CPC title