Semiconductor device and electronic equipment

Patent metadata

Field	Value
Publication number	US-10199414-B2
Application number	US-201715496614-A
Country	US
Kind code	B2
Filing date	Apr 25, 2017
Priority date	Feb 3, 2012
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

The present technology relates to a semiconductor device and electronic equipment in which a semiconductor device that suppresses the occurrence of noise by a leakage of light can be provided.
A semiconductor device is configured which includes a light-receiving element 34 , an active element for signal processing, and a light shielding structure 40 which is between the light-receiving element 34 and the active element to cover the active element and is formed of wirings 45 and 46 . The semiconductor device further includes a first substrate on which the light-receiving element is formed, a second substrate on which the active element is formed, and a wiring layer which has a light shielding structure by the wirings which is formed on the second substrate, and in which the second substrate can be bonded to the first substrate through the wiring layer.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a first substrate including a light-receiving element in a first semiconductor substrate;
a second substrate on the first substrate, the second substrate including:
an active element in a first direction in a second semiconductor substrate, and
a light shielding structure between the light-receiving element and the active element; and

buffer zones on both sides of the active element, wherein a width of each of the buffer zones is wider than a distance from the active element to the light shielding structure, and
wherein, in a cross-sectional view, the light shielding structure includes:
a first wiring layer that includes a first wiring and a second wiring;
a second wiring layer that includes a third wiring; and
an inter-wiring region between the first wiring and the second wiring,
wherein the inter-wiring region is above the active element, and wherein the third wiring overlaps the inter-wiring region.

2. The semiconductor device according to claim 1 , wherein the second semiconductor substrate is bonded to the first semiconductor substrate through the light shielding structure.

3. The semiconductor device according to claim 2 , wherein an origin of the second wiring is from a branch point of the first wiring, and wherein the light shielding structure has a first portion of the first wiring parallel to a second portion of the second wiring.

4. The semiconductor device according to claim 1 ,
wherein the active element is divided into a plurality of circuit blocks,
wherein a first region that corresponds to a circuit block of the plurality of circuit blocks is a light shielding target region, and
wherein a second region between the plurality of circuit blocks is a light shielding non-target region.

5. The semiconductor device according to claim 1 , wherein the light-receiving element is a photoelectric conversion element.

6. The semiconductor device according to claim 1 , wherein the light-receiving element is a high sensitivity analog element with a high sensitivity to light noises.

7. An electronic equipment, comprising:
a first substrate including a light-receiving element in a first semiconductor substrate;
a second substrate on the first substrate, the second substrate including:
an active element in a first direction in a second semiconductor substrate, and
a light shielding structure between the light-receiving element and the active element; and

buffer zones on both sides of the active element, wherein a width of each of the buffer zones is wider than a distance from the active element to the light shielding structure, and
wherein, in a cross-sectional view, the light shielding structure includes:
a first wiring layer that includes a first wiring and a second wiring;
a second wiring layer that includes a third wiring; and
an inter-wiring region between the first wiring and the second wiring,
wherein the inter-wiring region is above the active element, and
wherein the third wiring overlaps the inter-wiring region.

8. A semiconductor device, comprising:
a layer of lower wirings in a light shielding structure, wherein the layer of lower wirings comprises a first wiring and a second wiring;
a layer of upper wirings in the light shielding structure, wherein the layer of upper wirings comprises a third wiring;
a first active element in a first light shielding target region of a semiconductor substrate; and
buffer zones on both sides of the first active element, wherein a width of each of the buffer zones is wider than a distance from the first active element to the light shielding structure.

9. The semiconductor device according to claim 8 , wherein an inter wiring distance in a first direction in a cross-sectional view of the light shielding structure is a gap between the layer of lower wirings and the layer of upper wirings, wherein the third wiring of the layer of upper wirings overlays a portion of the second wiring of the layer of lower wirings by an amount of overlap, and wherein the amount of overlap is at least greater than the inter wiring distance.

10. The semiconductor device according to claim 8 , further comprising, in a cross-sectional view of the light shielding structure, an insulation between the first wiring of the layer of lower wirings and the second wiring of the layer of lower wirings.

11. The semiconductor device according to claim 8 , wherein an opening width in a cross-sectional view of the light shielding structure is a gap between the first wiring of the layer of lower wirings and the second wiring of the layer of lower wirings.

12. The semiconductor device according to claim 8 , further comprising a light-receiving element between an optical member and the layer of upper wirings.

13. The semiconductor device according to claim 12 , wherein the light-receiving element is a photodiode.

14. The semiconductor device according to claim 8 , wherein the layer of lower wirings is between the first active element and the layer of upper wirings.

15. The semiconductor device according to claim 14 , further comprising a light shielding non-target region of the semiconductor substrate, wherein the light shielding non-target region is between the first light shielding target region of the semiconductor substrate and a second light shielding target region of the semiconductor substrate.

16. The semiconductor device according to claim 15 , further comprising a second active element in the second light shielding target region.

17. The semiconductor device according to claim 15 , wherein an interlayer distance is a length from the first active element to the light shielding structure, and a buffer zone width is a distance from the first active element to the light shielding non-target region, and wherein the buffer zone width is larger than the interlayer distance.

18. An electronic equipment, comprising:
a semiconductor device, comprising:
a layer of lower wirings in a light shielding structure;
a layer of upper wirings in the light shielding structure;
a first active element in a first light shielding target region of a semiconductor substrate; and
buffer zones on both sides of the first active element, wherein a width of each of the buffer zones is wider than a distance from the first active element to the light shielding structure.

19. The semiconductor device according to claim 1 , wherein an amount of overlap between the third wiring and each of the first wiring and the second wiring is the same.

Assignees

• Sony Corp

Inventors

• Kobayashi Shoji
• Kudoh Yoshiharu
• Sano Takuya

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L31/0224

  Electricity · mapped topic