Array substrate and manufacturing method thereof, display panel and display device

Patent metadata

Field	Value
Publication number	US-10199406-B2
Application number	US-201615175700-A
Country	US
Kind code	B2
Filing date	Jun 7, 2016
Priority date	Jul 22, 2015
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

An array substrate and a manufacturing method thereof, a display panel and a display device are provided. The array substrate manufacturing method comprises: forming a source electrode and a drain electrode on a gate insulating layer; forming photoresist above the gate insulating layer and the source electrode and the drain electrode; etching the photoresist to form an opening region so as to expose the gate insulating layer between the source electrode and the drain electrode, and a part of the source electrode and a part of the drain electrode; and forming an active layer in the opening region, the active layer covering the exposed gate insulating layer, the part of the source electrode and the part of the drain electrode.

First claim

The invention claimed is:

1. An array substrate manufacturing method, comprising:
forming a source electrode and a drain electrode on a gate insulating layer;
forming photoresist above the gate insulating layer and the source electrode and the drain electrode;
etching the photoresist to form an opening region so as to expose the gate insulating layer between the source electrode and the drain electrode, and a part of the source electrode and a part of the drain electrode;
directly forming an active layer in the opening region, the active layer covering the exposed gate insulating layer, the part of the source electrode and the part of the drain electrode,
wherein a surface energy of the photoresist is greater than a surface energy of the gate insulating layer; and the array substrate manufacturing method further comprises: after forming the active layer in the opening region, removing the photoresist.

2. The array substrate manufacturing method according to claim 1 , wherein the forming the active layer in the opening region includes:
filling a semiconductor material in the opening region, so as to form the active layer.

3. The array substrate manufacturing method according to claim 2 , wherein the filling a semiconductor material in the opening region includes:
filling the semiconductor material in the opening region by ink-jet printing, silk-screen printing, blade coating or spin coating.

4. The array substrate manufacturing method according to claim 1 , wherein a length-width ratio of the opening region is 10:1 to 50:1, and a length-width ratio of the active layer is equal to that of the opening region.

5. The array substrate manufacturing method according to claim 3 , wherein under a condition that the semiconductor material is filled in the opening region by ink-jet printing so as to form the active layer, a width of the opening region is 5 μm to 50 μm.

6. The array substrate manufacturing method according to claim 3 , wherein under a condition that the semiconductor material is filled in the opening region by silk-screen printing, blade coating or spin coating, so as to form the active layer, a width of the opening region is 30 μm to 100 μm.

7. The array substrate manufacturing method according to claim 3 , after the filling the semiconductor material in the opening region by blade coating or spin coating so as to form the active layer, further comprising:
removing the semiconductor material outside the opening region.

8. The array substrate manufacturing method according to claim 1 , wherein the etching the photoresist to form the opening region includes:
etching the photoresist by dry etching or wet etching.

9. The array substrate manufacturing method according to claim 1 , wherein the photoresist is fluorinated photoresist.

10. The array substrate manufacturing method according to claim 1 , wherein the forming the active layer in the opening region further includes:
annealing the active layer, and setting a structure parameter of the active layer by controlling annealing time and annealing temperature.

11. The array substrate manufacturing method according to claim 2 , wherein the semiconductor material outside the opening region is removed while the photoresist is removed.

12. An array substrate manufacturing method, comprising:
forming a source electrode and a drain electrode on a gate insulating layer;
forming photoresist above the gate insulating layer and the source electrode and the drain electrode;
etching the photoresist to form an opening region so as to expose the gate insulating layer between the source electrode and the drain electrode, and a part of the source electrode and a part of the drain electrode;
forming an active layer in the opening region, the active layer covering the exposed gate insulating layer, the part of the source electrode and the part of the drain electrode,
wherein the photoresist is a fluorinated photoresist, and a surface energy of the fluorinated photoresist is greater than a surface energy of the gate insulating layer; and the array substrate manufacturing method further comprises: after forming the active layer in the opening region, removing the photoresist.

Assignees

• Boe Technology Group Co Ltd
• Univ Shanghai Jiaotong

Inventors

• Huang Wei
• Zhao Jiaqing
• Feng Linrun
• Tang Wei
• Guo Xiaojun

Classifications

• H01L27/127

  Electricity · mapped topic

• H01L27/1292 Primary

  Electricity · mapped topic

• H01L29/4908

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• H01L29/66765

  Electricity · mapped topic