Wire bond free wafer level LED

Patent metadata

Field	Value
Publication number	US-10199360-B2
Application number	US-201715449510-A
Country	US
Kind code	B2
Filing date	Mar 3, 2017
Priority date	Nov 14, 2007
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.

First claim

We claim:

1. A device comprising:
a plurality of active regions, each of which is between an n-type layer and a p-type layer, wherein one of said n-type or p-type layers comprises the primary emission surface;
one or more n-electrodes and corresponding one or more vias;
one or more p-electrodes, wherein said n-electrodes and p-electrodes are in electrical contact with said active regions, and wherein said n-electrodes and p-electrodes are on the side of said active region opposite said primary emission surface;
one or more n-pads in electrical contact with corresponding said one or more n-electrodes; and
one or more spacer elements, wherein said one or more spacer elements is partially between said one or more n-pads and a portion of said one or more n-electrodes nearest said corresponding one or more n-pads.

2. The device of claim 1 , comprising a single n-type layer and a plurality of p-type layers, wherein each of said active regions are between said single n-type layer and a respective one of said plurality of p-type layers.

3. The device of claim 2 , wherein said n-type layer comprises the primary emission surface, and said n-electrodes contacting said n-type layer between said active regions.

4. The device of claim 2 , wherein said n-electrodes contact said n-type layer between said p-type layers.

5. The device of claim 1 , wherein each of said one or more n-electrodes is in electrical contact with said n-type layer.

6. The device of claim 1 , comprising a plurality of p-type layers wherein each of said p-electrodes is in contact with a respective one of said p-type layers.

7. The device of claim 1 , further comprising a plurality of spacer elements coupled to the n-electrode and the p-electrode, such that each of said spacer elements electrically isolates one of said n-electrodes from one of said p-electrodes.

8. The device of claim 7 , wherein each of said n-electrodes and said p-electrodes extend laterally over at least one of said spacer elements.

9. The device of claim 1 , further comprising a wavelength conversion layer adjacent said primary emission surface.

10. The device of claim 1 , wherein said n-electrodes and said p-electrodes have surfaces that are coplanar.

11. A device comprising:
a plurality of active regions each having a primary emission surface;
multiple n-electrodes accessible from a surface opposite the primary emission surface and each providing an electrical path to one or more of said active regions; and
multiple p-electrodes on the same side of said active regions as said n-electrodes, each of said p-electrodes also accessible from a surface opposite the primary emission surface and providing an electrical path to one or more of said active regions, wherein said n-electrodes and said p-electrodes have surfaces that are coplanar, wherein a cross-section of each of said n-electrodes widens toward said surface opposite the primary emission surface.

12. A device of claim 11 , wherein each of said active regions is between a respective one of a plurality of n-type layers and a respective one of plurality of p-type layers.

13. The device of claim 12 , wherein each of said p-type layers is each of said active regions primary emission surface.

14. The device of claim 12 , wherein each of said n-type layers is each of said active regions primary emission surface.

15. The device of claim 11 , wherein each of said active regions comprises a flip-chip light emitting diode (LED) structure.

16. The device of claim 12 , wherein each of said multiple n-electrodes is in electrical contact with one of said n-type layers and each of said p-electrodes is in contact with a respective one of said p-type layers.

17. The device of claim 11 , further comprising a plurality of spacer elements each of which electrically isolates one of said n-electrodes from one of said p-electrodes.

18. The device of claim 7 , wherein each of said n-electrodes and said p-electrodes extend laterally over at least one of said spacer elements.

19. The device of claim 1 , further comprising one or more wavelength conversion layers adjacent said active regions.

20. A device comprising:
a plurality of active regions each having a primary emission surface;
multiple n-electrodes accessible from a surface opposite the primary emission surface and each providing an electrical path to one or more of said active regions;
multiple p-electrodes on the same side of said active regions as said n-electrodes, each of said p-electrodes also accessible from a surface opposite the primary emission surface and providing an electrical path to one or more of said active regions, wherein said n-electrodes and said p-electrodes provide primary mechanical support for said device;
multiple n-pads in electrical contact with corresponding said n-electrodes; and
one or more spacer elements, wherein said one or more spacer elements is partially between said n-pads and a portion of said n-electrodes nearest said corresponding one or more n-pads.

Assignees

• Cree Inc

Inventors

• Keller Bernd
• Chitnis Ashay
• Medendorp Jr Nicholas W
• Ibbetson James
• Batres Max

Classifications

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H01L2224/45099

  Electricity · mapped topic