Semiconductor devices including stacked semiconductor chips

Patent metadata

Field	Value
Publication number	US-10199355-B2
Application number	US-201615358579-A
Country	US
Kind code	B2
Filing date	Nov 22, 2016
Priority date	Nov 27, 2015
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A semiconductor device includes a chip stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer disposed on the first circuit layer and including a first metal pad electrically connected to the first circuit layer. The second semiconductor chip includes a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer disposed on the second circuit layer and including a second metal pad electrically connected to the second circuit layer. The first connecting layer faces the second connecting layer. The first and second metal pads are in contact with each other to couple the first and second semiconductor chips to each other.

First claim

What is claimed is:

1. A semiconductor device comprising:
a chip stack structure comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip,
wherein the first semiconductor chip comprises:
a first substrate;
a first circuit layer on a front surface of the first substrate; and
a first connecting layer on the first circuit layer, the first connecting layer comprising a first metal pad electrically connected to the first circuit layer,
wherein the second semiconductor chip comprises:
a second substrate;
a second circuit layer on a front surface of the second substrate; and
a second connecting layer on the second circuit layer, the second connecting layer comprising a second metal pad electrically connected to the second circuit layer,
wherein the first connecting layer and the second connecting layer face each other,
wherein the first metal pad and the second metal pad are in contact with each other to couple the first and second semiconductor chips to each other,
wherein the first metal pad comprises a plurality of first metal pad portions separated from each other by first partitions, and
wherein the second metal pad comprises a plurality of second metal pad portions separated from each other by second partitions.

2. The semiconductor device of claim 1 , wherein each of the first and second metal pads has a rectangular shape when viewed in a plan view, and
wherein the first and second metal pads intersect each other.

3. The semiconductor device of claim 2 , wherein the plurality of first metal pad portions are arranged in a long-axis direction of the first metal pad,
wherein each of the first partitions is between respective ones of the plurality of first metal pad portions that are adjacent each other,
wherein the plurality of second metal pad portions are arranged in a long-axis direction of the second metal pad, and
wherein each of the second partitions is between respective ones of the plurality of second metal pad portions that are adjacent each other.

4. The semiconductor device of claim 3 , wherein the first metal pad has a first length in the long-axis direction of the first metal pad and a first width in a short-axis direction of the first metal pad, and
wherein a ratio of the first length to the first width is 2 or greater.

5. The semiconductor device of claim 1 , wherein the first connecting layer further comprises:
a first upper insulating layer surrounding the first metal pad; and
a first bonding insulating layer on the first upper insulating layer and exposing the first metal pad,
wherein the second connecting layer further comprises:
a second upper insulating layer surrounding the second metal pad; and
a second bonding insulating layer on the second upper insulating layer and exposing the second metal pad, and
wherein the first bonding insulating layer is in contact with the second bonding insulating layer.

6. The semiconductor device of claim 5 , wherein an air gap is between the first metal pad and the second bonding insulating layer or between the second metal pad and the first bonding insulating layer.

7. The semiconductor device of claim 5 , wherein the first circuit layer comprises: a first integrated circuit; and first metal lines electrically connected to the first integrated circuit,
wherein the second circuit layer comprises: a second integrated circuit; and second metal lines electrically connected to the second integrated circuit,
wherein the first metal pad penetrates the first upper insulating layer so as to contact at least one of the first metal lines, and
wherein the second metal pad penetrates the second upper insulating layer so as to contact at least one of the second metal lines.

8. The semiconductor device of claim 1 , wherein the first semiconductor chip is a logic chip, and
wherein the second semiconductor chip is a pixel array chip further comprising:
at least one photoelectric conversion part in the second substrate; and
a micro lens on a back surface of the second substrate,
wherein the back surface of the second substrate is opposite to the front surface of the second substrate.

9. A semiconductor device comprising:
a first semiconductor chip comprising a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer on the first circuit layer; and
a second semiconductor chip comprising a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer on the second circuit layer,
wherein the first connecting layer comprises a first metal pad electrically connected to the first circuit layer,
wherein the first metal pad has a rectangular planar shape,
wherein the first metal pad comprises: a plurality of first metal pad portions arranged in a long-axis direction of the first metal pad; and first partitions between respective ones of the plurality of first metal pad portions ,
wherein the second connecting layer comprises a second metal pad electrically connected to the second circuit layer,
wherein the second metal pad has a rectangular planar shape,
wherein the second metal pad comprises: a plurality of second metal pad portions arranged in a long-axis direction of the second metal pad; and second partitions between respective ones of the plurality of second metal pad portions,
wherein the second semiconductor chip is disposed on the first semiconductor chip in such a way that the first and second connecting layers are in contact with each other and the first and second metal pads intersect each other.

10. The semiconductor device of claim 9 , wherein at least one of the plurality of first metal pad portions is in contact with at least one of the plurality of second metal pad portions in a region of the first and second metal pads in which the first and second metal pads intersect.

11. The semiconductor device of claim 9 , wherein the plurality of first metal pad portions are spaced apart from each other and are insulated from each other by the first partitions, and
wherein the plurality of second metal pad portions are spaced apart from each other and are insulated from each other by the second partitions.

12. The semiconductor device of claim 9 , wherein the first circuit layer comprises:
a first integrated circuit;
first interlayer insulating layers covering the first integrated circuit; and
first metal lines in the first interlayer insulating layers,
wherein the second circuit layer comprises:
a second integrated circuit;
second interlayer insulating layers covering the second integrated circuit; and
second metal lines disposed in the second interlayer insulating layers, and
wherein the first and second connecting layers are between the first interlayer insulating layers and the second interlayer insulating layers.

13. The semiconductor device of claim 12 , wherein the first connecting layer further comprises: a first upper insulating layer on the first interlayer insulating layers; and a first bonding insulating layer covering a surface of the first upper insulating layer and exposing the first metal pad,
wherein the second connecting layer further comprises: a second upper insulating layer on the second interlayer insulating layers; and a second bonding insulating layer covering a surface of the second upper insulating layer and exposing the second metal pad,
wherein the first bonding insulating layer is in contact with the second bonding insulating layer,
wherein the first metal pad penetrates the first upper insulating layer so as to be connected directly to at least one of the fi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Donghyun
• Kwon Doowon

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title