Method for fabricating a metal high-k gate stack for a buried recessed access device

Patent metadata

Field	Value
Publication number	US-10199227-B2
Application number	US-201715606574-A
Country	US
Kind code	B2
Filing date	May 26, 2017
Priority date	May 31, 2013
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain region in the substrate, depositing a dummy gate in each of the plurality of gate trenches, filling the plurality of gate trenches with an oxide layer, removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches, depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches, depositing a second oxide layer on the metal gate and forming a contact on the source/drain.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a plurality of trenches formed in the substrate, wherein the trenches extend from a first surface of the substrate to a first depth, and wherein each trench contains a gate at an end of the trench opposite the first surface of the substrate;
a plurality of regions formed in the substrate, wherein each region in the plurality of regions is between respective ones of the trenches and extends from the first surface of the substrate to a second depth, wherein each region contains a source/drain region at an end of the region opposite the first surface of the substrate, and wherein the first depth is greater than the second depth; and
a plurality of oxide layers, each oxide layer being formed on a respective gate in each trench, wherein a portion of at least one of the oxide layers that is furthest away from the first surface is at a third depth, wherein a portion of at least one of the gates that is furthest away from the first surface is at a fourth depth greater than the third depth.

2. The semiconductor device of claim 1 , wherein each region further contains an electrode adjacent the first surface of the substrate.

3. The semiconductor device of claim 1 , wherein each trench further contains a dielectric layer, and wherein the dielectric layer separates the gate and the oxide layer from adjacent ones of the regions.

4. The semiconductor device of claim 3 , wherein a portion of at least one of the regions that is furthest away from the first surface is at a fifth depth, and wherein the fifth depth is greater than the third depth.

5. The semiconductor device of claim 4 , wherein the third depth is greater than a depth to which each of the electrodes extends.

6. The semiconductor device of claim 4 , wherein each region further contains a silicide layer between the electrode and the source/drain region.

7. The semiconductor device of claim 6 , wherein the silicide layer is formed from the source/drain regions.

8. The semiconductor device of claim 7 , wherein each of the electrodes is formed from a metal layer, and wherein each of the gates is a metal gate.

Assignees

• Sony Corp
• Sony Semiconductor Solutions Corp

Inventors

• Mayuzumi Satoru
• Fischer Mark
• Violette Michael

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01316

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al · CPC title

• H10D64/013 Primary

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title