Non-volatile memory devices, operating methods thereof and memory systems including the same

Patent metadata

Field	Value
Publication number	US-10199116-B2
Application number	US-201715664303-A
Country	US
Kind code	B2
Filing date	Jul 31, 2017
Priority date	Feb 17, 2010
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

First claim

What is claimed is:

1. A method of operating a nonvolatile memory device including a plurality of memory cell strings, each of the plurality of memory cell strings including a plurality of memory cells stacked on a substrate in a direction vertical to the substrate, the plurality of memory cells being divided into a first portion and a second portion, the second portion being stacked over the first portion, the method comprising:
programming a first selected memory cell located in the first portion by applying a first initial program voltage on the first selected memory cell, a level of the first initial program voltage being higher as a distance between the first selected memory cell and the substrate being longer;
verifying the first selected memory cell to determine programming pass or programming fail;
programming a second selected memory cell located in the second portion by applying a second initial program voltage on the second selected memory cell, a level of the second initial program voltage being higher as a distance between the second selected memory cell and the substrate being longer; and
verifying the second selected memory cell to determine programming pass or programming fail,
wherein, the level of the first initial program voltage applied to the first selected memory cell located at top of the first portion is higher than the level of the second initial program voltage applied to the second selected memory cell located at bottom of the second portion.

2. The method of claim 1 , wherein the method further includes applying a first increased program voltage on the first selected memory cell based on a result of verifying the first selected memory cell and applying a second increased program voltage on the second selected memory cell based on the result of verifying the second selected memory cell.

3. The method of claim 2 , wherein the first increased program voltage is higher than the first initial program voltage by a first increment and the second increased program voltage is higher than the second initial program voltage by a sccond increment.

4. The method of claim 3 , wherein a magnitude of the first increment becomes greater as the distance between the first selected memory cell and the substrate becomes longer, and a magnitude of the second increment becomes greater as the distance between the second selected memory cell and the substrate becomes longer, and the first increment of the first increased program voltage applied to the first selected memory cell located at top of the first portion is greater than the second increment of the second increased program voltage applied to the second selected memory cell located at bottom of the second portion.

5. The method of claim 4 , wherein a first hole diameter of the first selected memory cell becomes larger as the distance between the first selected memory cell and the substrate becomes longer, and a second hole diameter of the second selected memory cell becomes larger as a distance between the second selected memory cell and the substrate becomes longer, and the first hole diameter of the first selected memory cell located at top of the first portion is greater than the second hole diameter of the second selected memory cell located at bottom the second portion.

6. The method of claim 5 , wherein channel holes of the first selected memory cell and the second selected memory cell are formed through separate etching process steps respectively.

7. The method of claim 1 , wherein the method further includes applying a plurality of first pass voltages to a plurality of first unselected memory cells of the first portion and applying a plurality of second pass voltages to a plurality of second unselected memory cells of the second portion while applying the first initial program voltage or the second initial program voltage to the first selected memory cell or the second selected memory cell.

8. The method of claim 7 , wherein at least a first portion of the first pass voltages have a different level from the rest of the first pass voltages while the first portion of the first pass voltages within the first portion have a same level, and at least a second portion of the second pass voltages have a different level from the rest of the second pass voltages while the second portion of the second pass voltages within the second portion have a same level.

9. The method of claim 7 , wherein the levels of the first pass voltages are increased as the plurality of first unselected memory cells are located more distantly from the substrate, and the levels of the second pass voltages are increased as the plurality of the second unselected memory cells are located more distantly from the substrate, and a level of a first pass voltage which is applied to the first unselected memory cell, among the plurality of first unselected voltage that is located at top of the first portion is higher than a level of a second pass voltage which is applied to the second unselected memory cell, among the plurality of second unselect voltage, that is located at bottom of the second portion.

10. The method of claim 7 , wherein each of the plurality of first pass voltages is different from one another, and each of the plurality of second pass voltages is different from one another.

11. The method of claim 1 , wherein the method further includes performing a read operation by applying a plurality of first read unselect voltages on a plurality of first read unselect memory cells of the first portion and by applying a plurality of second read unselect voltages on a plurality of second read unselect memory cells of the second portion.

12. The method of claim 11 , wherein at least a portion of the first read unselect voltages are different from a rest of first read unselect voltages according to locations of the first read unselect memory cells to which the first read unselect voltages are applied, and at least a portion of the second read unselect voltages are different from a rest of second read unselect voltages according to locations of the second read unselect memory cells to which the second read unselect voltages are applied.

13. The method of claim 12 , wherein levels of the first read unselect voltages are increased as the plurality of first read unselect memory cells are located more distantly from the substrate, and the levels of the second read unselect voltages are increased as the plurality of second read unselect memory cells are located more distantly from the substrate, and a level of a first read unselect voltage, among the plurality of first read unselect voltage, which is applied to a first read unselect memory cell among the plurality of first read unselect memory cells, that is located at a top of the first portion is higher than a level of a second read unselect voltage, among the plurality of second read unselect voltages, which is applied to a second read unselect memory cell, among the plurality of second read unselect memory cells, that is located at a bottom of the second portion.

14. The method of claim 1 , wherein the method further includes performing a erase operation by applying a plurality of first erase voltages on a plurality of first erase memory cells of the first portion and by applying a plurality of second erase voltages on a plurality of second erase memory cells of the second portion.

15. The method of claim 14 , wherein at least a portion of the first erase voltages are different from a rest of first erase voltages according to locations of the first erase memory cells to which the first erase voltages are applied, and at least a portion of the second erase volta

Assignees

• Shim Sun Il
• Jang Jae Hoon
• Chae Donghyuk
• Lim Youngho
• Kim Hansoo
• Jeong Jaehun
• Samsung Electronics Co Ltd

Inventors

• Shim Sun-Il
• Jang Jae-Hoon
• Chae Donghyuk
• Lim Youngho
• Kim Hansoo
• Jeong Jaehun

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title