Retention minimum voltage determination techniques

Patent metadata

Field	Value
Publication number	US-10199091-B2
Application number	US-201615373048-A
Country	US
Kind code	B2
Filing date	Dec 8, 2016
Priority date	Dec 8, 2016
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.

First claim

The invention claimed is:

1. An apparatus, comprising:
a semiconductor chip, comprising:
a memory comprising multiple storage cells, said storage cells to receive a supply voltage; and,
retention voltage determination circuitry, said retention voltage determination circuitry to determine a level of said supply voltage at which said storage cells are able to retain their respective data, said retention voltage determination circuitry comprising a storage cell to receive said supply voltage during a stress mode of said retention voltage determination circuitry, said retention voltage determination circuitry to apply a voltage that is less than said supply voltage to said storage cell during a measurement mode of said retention voltage determination circuitry to cause said storage cell to more weakly retain its stored information than said storage cells during said measurement mode.

2. The apparatus of claim 1 wherein said retention voltage determination circuitry comprises a first supply current path and a second supply current path, the first supply current path to impose negligible supply voltage drop, the second supply current path to impose a non-negligible supply voltage drop, the first supply current path to be enabled during the stress mode, the second supply current path to be enabled during the measurement mode.

3. The apparatus of claim 2 wherein the second current path comprises one or more diodes.

4. The apparatus of claim 1 wherein said storage cell has more pull-up transistors than respective ones of said storage cells.

5. The apparatus of claim 1 wherein said retention voltage determination circuitry comprises different numbers of transistors on different legs of said supply voltage retention circuitry.

6. The apparatus of claim 1 wherein said semiconductor chip comprises a power management controller and said retention voltage determination circuitry is coupled to said power management controller.

7. The apparatus of claim 6 wherein said semiconductor chip comprises a plurality of retention voltage determination circuits for said memory coupled to said power management controller, said retention voltage determination circuits including said retention voltage determination circuitry.

8. An apparatus, comprising:
a semiconductor chip, comprising:
a memory comprising multiple storage cells, said storage cells to receive a supply voltage; and,
retention voltage determination circuitry, said retention voltage determination circuitry to determine a level of said supply voltage at which said storage cells are able to retain their respective data, said retention voltage determination circuitry comprising a plurality of storage cells to receive said supply voltage during a stress mode of said retention voltage determination circuitry, said retention voltage retention determination circuitry to apply a voltage that is less than said supply voltage to said plurality of storage cells during a measurement mode of said retention voltage determination circuitry cause said plurality of storage cells to more weakly retain their stored information than said memory's multiple storage cells during said measurement mode, said plurality of storage cells having their respective data output nodes coupled together.

9. The apparatus of claim 8 wherein said retention voltage determination circuitry comprises a first supply current path and a second supply current path, the first supply current path to impose negligible supply voltage drop, the second supply current path to impose a non-negligible supply voltage drop, the first supply current path to be enabled during the stress mode, the second supply current path to be enabled during the measurement mode.

10. The apparatus of claim 9 wherein the second current path comprises one or more diodes.

11. The apparatus of claim 8 wherein said plurality of storage cells each comprise more pull-up transistors than respective ones of said memory's multiple storage cells.

12. The apparatus of claim 8 wherein said retention voltage determination circuitry comprises different numbers of transistors on different legs of said retention voltage determination circuitry.

13. The apparatus of claim 8 wherein said semiconductor chip comprises a power management controller and said retention voltage determination circuitry is coupled to said power management controller.

14. A computing system, comprising:
a semiconductor chip, comprising:
a plurality of processing cores;
a memory controller;
a memory comprising multiple storage cells, said storage cells to receive a supply voltage; and,
retention voltage determination circuitry, said retention voltage determination circuitry to determine a level of said supply voltage at which said storage cells are able to retain their respective data, said retention voltage determination circuitry comprising a storage cell to receive said supply voltage during a stress mode of said retention voltage determination circuitry, said retention voltage determination circuitry to apply a voltage that is less than said supply voltage to said storage cell during a measurement mode of said retention voltage determination circuitry to cause said storage cell to more weakly retain its stored information than said storage cells during said measurement mode, said measurement mode to determine a minimum supply voltage for said storage cells.

15. The computing system of claim 14 wherein said retention voltage determination circuitry comprises a first supply current path and a second supply current path, the first supply current path to impose negligible supply voltage drop, the second supply current path to impose a non-negligible supply voltage drop, the first supply current path to be enabled during the stress mode, the second supply current path to be enabled during the measurement mode.

16. The computing system of claim 15 wherein the second current path comprises one or more diodes.

17. The computing system of claim 14 wherein said storage cell has more pull-up transistors than respective ones of said storage cells.

18. The computing system of claim 14 wherein said semiconductor chip comprises a power management controller and said supply voltage retention circuitry is coupled to said power management controller.

19. The computing system of claim 14 wherein said memory is to implement a cache for said processing cores.

Assignees

• Intel Corp

Inventors

• Cho Minki
• Kulkarni Jaydeep
• Tokunaga Carlos
• Khellah Muhammad
• Tschanz James

Classifications

• G11C2029/1206

  Location of test circuitry on chip or wafer · CPC title

• G11C29/50016

  of retention · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C11/4125

  Cells incorporating circuit means for protecting against loss of information · CPC title

• G11C29/24

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title