Max pooling in a matrix processing architecture

US10198401B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10198401-B2
Application numberUS-201615395786-A
CountryUS
Kind codeB2
Filing dateDec 30, 2016
Priority dateDec 30, 2016
Publication dateFeb 5, 2019
Grant dateFeb 5, 2019

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Abstract

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In one embodiment, an apparatus comprises a multi-dimensional memory and a plurality of processing elements to perform a matrix operation, wherein the matrix operation comprises a max pooling operation on one or more matrix operands. The plurality of processing elements comprises one or more matrix processors, and the plurality of processing elements is configured to: receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands; extract the one or more matrix operands from the matrix data; perform the max pooling operation using the one or more matrix operands; and obtain a result of the max pooling operation.

First claim

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What is claimed is: 1. An apparatus, comprising: a multi-dimensional memory; a plurality of processing elements to perform a matrix operation, wherein: the plurality of processing elements comprises one or more matrix processors; and the matrix operation comprises a backward pooling operation on one or more matrix operands, wherein the one or more matrix operands comprise a max value matrix associated with an original matrix, and wherein the backward pooling operation comprises an operation to create a reconstructed matrix by partially reconstructing the original matrix using the max value matrix; wherein the plurality of processing elements is configured to: receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands; extract the one or more matrix operands from the matrix data; perform the backward pooling operation using the one or more matrix operands, wherein the plurality of processing elements configured to perform the backward pooling operation is further configured to: identify a max value entry from the max value matrix; create a partial matrix based on the max value entry, wherein the partial matrix comprises a portion of the reconstructed matrix; determine that one or more elements of the partial matrix will not be modified; and write the one or more elements of the partial matrix to the multi-dimensional memory; and obtain a result of the backward pooling operation. 2. The apparatus of claim 1 , wherein the plurality of processing elements is further configured to perform a forward pooling operation. 3. The apparatus of claim 2 , wherein the forward pooling operation is associated with a forward propagation operation in a neural network. 4. The apparatus of claim 2 , wherein the forward pooling operation comprises an operation to reduce a size of a matrix operand. 5. The apparatus of claim 1 , wherein the max value entry comprises a maximum value and an index. 6. The apparatus of claim 1 , further comprising a FIFO memory to store one or more elements of the reconstructed matrix. 7. The apparatus of claim 6 , wherein the FIFO memory comprises one or more status bits to track whether one or more entries in the FIFO memory have been modified. 8. The apparatus of claim 1 , wherein the max value matrix is an output of a forward pooling operation. 9. The apparatus of claim 1 , wherein the max value matrix comprises one or more value-index pairs, wherein the one or more value-index pairs each comprise a maximum value and an index. 10. The apparatus of claim 1 , wherein the backward pooling operation is associated with a backward propagation operation in a neural network. 11. A method, comprising: performing a matrix operation, wherein the matrix operation comprises a backward pooling operation on one or more matrix operands, wherein the one or more matrix operands comprise a max value matrix associated with an original matrix, wherein the backward pooling operation comprises an operation to create a reconstructed matrix by partially reconstructing the original matrix using the max value matrix, and wherein performing the matrix operation comprises: receiving matrix data from a multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands; extracting the one or more matrix operands from the matrix data; performing the backward pooling operation using the one or more matrix operands, wherein performing the backward pooling operation comprises: identifying a max value entry from the max value matrix; creating a partial matrix based on the max value entry, wherein the partial matrix comprises a portion of the reconstructed matrix; determining that one or more elements of the partial matrix will not be modified; and writing the one or more elements of the partial matrix to the multi-dimensional memory; and obtaining a result of the backward pooling operation. 12. The method of claim 11 , further comprising storing one or more elements of the reconstructed matrix in a FIFO memory, wherein the FIFO memory comprises one or more status bits to track whether one or more entries in the FIFO memory have been modified. 13. A system, comprising: a plurality of memory elements, wherein the plurality of memory elements comprises a multi-dimensional memory; and a plurality of processing elements to perform a matrix operation, wherein: the plurality of processing elements comprises a host processor and one or more matrix processing chips; and the matrix operation comprises a backward pooling operation on one or more matrix operands, wherein the one or more matrix operands comprise a max value matrix associated with an original matrix, and wherein the backward pooling operation comprises an operation to create a reconstructed matrix by partially reconstructing the original matrix using the max value matrix; wherein the plurality of processing elements is configured to: receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands; extract the one or more matrix operands from the matrix data; perform the backward pooling operation using the one or more matrix operands, wherein the plurality of processing elements configured to perform the backward pooling operation is further configured to: identify a max value entry from the max value matrix; create a partial matrix based on the max value entry, wherein the partial matrix comprises a portion of the reconstructed matrix; determine that one or more elements of the partial matrix will not be modified; and write the one or more elements of the partial matrix to the plurality of memory elements; and obtain a result of the backward pooling operation. 14. The system of claim 13 , wherein each matrix processing chip comprises a plurality of matrix processing clusters. 15. The system of claim 14 , wherein each matrix processing cluster comprises a plurality of matrix processing units. 16. The system of claim 14 , wherein each matrix processing cluster comprises a plurality of memory resource blocks. 17. At least one non-transitory machine accessible storage medium having instructions stored thereon, the instructions, when executed on a machine, cause the machine to: perform a matrix operation, wherein the matrix operation comprises a backward pooling operation on one or more matrix operands, wherein the one or more matrix operands comprise a max value matrix associated with an original matrix, wherein the backward pooling operation comprises an operation to create a reconstructed matrix by partially reconstructing the original matrix using the max value matrix, and wherein the instructions that cause the machine to perform the matrix operation further cause the machine to: receive matrix data from a multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands; extract the one or more matrix operands from the matrix data; perform the backward pooling operation using the one or more matrix operands, wherein the instructions that cause the machine to perform the backward pooling operation further cause the machine to: identify a max value entry from the max value matrix; create a partial matrix based on the max value entry, wherein the partial matrix comprises a portion of the reconstructed matrix; determine that one or more elements of the partial matrix will not be modified; and write the one or more elements of the partial matrix to the multi-dimensional memory; and obt

Assignees

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Classifications

  • G06N3/045Primary

    Combinations of networks · CPC title

  • Learning methods · CPC title

  • G06F17/16Primary

    Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

  • Convolutional networks [CNN, ConvNet] · CPC title

  • G06V10/82Primary

    using neural networks · CPC title

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What does patent US10198401B2 cover?
In one embodiment, an apparatus comprises a multi-dimensional memory and a plurality of processing elements to perform a matrix operation, wherein the matrix operation comprises a max pooling operation on one or more matrix operands. The plurality of processing elements comprises one or more matrix processors, and the plurality of processing elements is configured to: receive matrix data from t…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06N3/045. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 05 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).