Testing device

Patent metadata

Field	Value
Publication number	US-10197621-B2
Application number	US-201414297897-A
Country	US
Kind code	B2
Filing date	Jun 6, 2014
Priority date	Jun 7, 2013
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A testing device includes a system circuit board, a first chip component, a supporting structure, a circuit board and an interposer. The system circuit board has a surface where the first chip component is disposed. The first chip component is connected to the system circuit board. The supporting structure is disposed on the surface and surrounds the first chip component; the circuit board is fixed on the supporting structure and keeps distance from the first chip component. The circuit board has a connector for connecting to a chip component that is to be tested. The interposer is located between the circuit board and the first chip component. The circuit board is connected to the first chip component via the interposer. The first chip component need not connect to the chip component to be tested, so is less liable to be damaged by the frequent testing.

First claim

What is claimed is:

1. A testing device for testing a chip component to be tested, the testing device comprising:
a system circuit board having a surface;
a first chip component, disposed on the surface of the system circuit board and electrically connected to the system circuit board;
a supporting structure, disposed on the surface and at least surrounding the first chip component;
a circuit board, fixed on the supporting structure and being separated from the first chip component, wherein the circuit board has a connector for electrically connecting to the chip component to be tested; and
an interposer, located between the circuit board and the first chip component, wherein the circuit board is electrically connected to the first chip component via the interposer.

2. The testing device of claim 1 , wherein the interposer has a substrate, a plurality of first conductive resilient sheets and a plurality of second conductive resilient sheets; the substrate has a first surface and a second surface opposite to each other; the first conductive resilient sheets are disposed on the first surface, the second conductive resilient sheets are disposed on the second surface, and the first conductive resilient sheets are electrically connected to the second conductive resilient sheets respectively; each of the circuit board and the first chip component has a plurality of contacts, and the first conductive resilient sheets make contact with the contacts of the circuit board respectively, and the second conductive resilient sheets make contact with the contacts of the first chip component respectively.

3. The testing device of claim 1 , wherein the interposer has a substrate, a plurality of first conductive resilient sheets and a plurality of bumps; the substrate has a first surface and a second surface opposite to each other; the first conductive resilient sheets are disposed on the first surface, the bumps are disposed on the second surface, and the first conductive resilient sheets are electrically connected to the bumps respectively; each of the circuit board and the first chip component has a plurality of contacts, the first conductive resilient sheets make contact with the contacts of the circuit board respectively, and the bumps make contact with the contacts of the first chip component respectively.

4. The testing device of claim 3 , wherein the substrate has a plurality of recesses which are disposed on the first surface, and end portions of the first conductive resilient sheets are sunk into the recesses respectively.

5. The testing device of claim 2 , wherein the substrate has a plurality of recesses which are disposed on the first surface, and end portions of the first conductive resilient sheets are sunk into the recesses respectively.

6. The testing device of claim 2 , wherein the substrate has a plurality of recesses which are disposed on the second surface, and end portions of the second conductive resilient sheets are sunk into the recesses respectively.

7. The testing device of claim 1 , wherein the circuit board further has a first rigid portion, a flexible portion and a second rigid portion; the flexible portion has two sides which are connected to the first rigid portion and the second rigid portion respectively; the first rigid portion is fixed on the supporting structure, and the connector is disposed on the second rigid portion.

8. The testing device of claim 7 , wherein the connector is a socket connector.

9. The testing device of claim 8 , wherein the connector is a package-on-package socket connector.

10. The testing device of claim 1 , wherein the connector is a socket connector.

11. The testing device of claim 10 , wherein the connector is a package-on-package socket connector.

12. The testing device of claim 1 , wherein the chip component to be tested is a memory chip.

13. The testing device of claim 1 , wherein the connector of the circuit board is separated from the first chip component in a direction which is perpendicular to a normal of the surface of the system circuit board.

14. A device for testing a target chip component, the device comprising:
a system circuit board having a surface;
a first chip component that is disposed on the surface of the system circuit board and electrically connected to the system circuit board;
a support that is disposed on the surface of and surrounds the first chip component;
a circuit board fixed on the support and separated from the first chip component; and
an interposer disposed between the circuit board and the first chip component,
wherein the circuit board is electrically connected to the first chip component via the interposer, and
wherein the circuit board includes a connector configured to electrically connect to the target chip component that is to be tested.

Assignees

• Kingston Digital Inc

Inventors

• Chen David
• Ong Chengvee
• Yu Chichih

Classifications

• G11C2029/5602

  Interface to device under test · CPC title

• G11C29/56016

  Apparatus features · CPC title

• G01R31/2863 Primary

  Contacting devices, e.g. sockets, burn-in boards or mounting fixtures (in general G01R1/04) · CPC title