System and method for ripple-free AC power determination

Patent metadata

Field	Value
Publication number	US-10197605-B2
Application number	US-201514669232-A
Country	US
Kind code	B2
Filing date	Mar 26, 2015
Priority date	Mar 26, 2015
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A power metering circuit includes a current input path for receiving an analog current input at a first analog to digital converter; a voltage input path for receiving an analog voltage input at a second analog to digital converter; a multiplier configured to multiply an output of the current input path and the voltage input path; a notch filter configured to receive an output of the multiplier, the notch filter having a stop band based on a line frequency; and a control circuit for setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a multiple of the line frequency.

First claim

What is claimed is:

1. A power metering circuit, comprising: a current input path for receiving an analog current input at a first analog to digital converter; a voltage input path for receiving an analog voltage input at a second analog to digital converter; a multiplier configured to multiply an output of the current input path and the voltage input path; a notch filter configured to receive an output of the multiplier, the notch filter having a stop band based on a line frequency; and a control circuit for setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a multiple of the line frequency, wherein the control circuit comprises a frequency detector and a programmable oscillator configured to receive an output of the frequency detector and to generate said sampling frequency, and wherein the frequency detector comprises a low pass filterfollowed by a zero-crossing detector and frequency counter.

2. A power metering circuit in accordance with claim 1 , wherein a number of clock periods detected is a power of 2 multiple of the line frequency.

3. A power metering circuit in accordance with claim 1 , the current input path and the voltage input path each including a highpass filter.

4. A power metering circuit in accordance with claim 3 , wherein the voltage input path includes a selectable phase shifter.

5. A power metering circuit in accordance with claim 1 , including an output pulse width modulator.

6. A power metering circuit, comprising: a first input path for receiving one of an analog current input or an analog voltage input at a first analog to digital converter; a second input path for receiving another of the analog voltage input or the analog current input at a second analog to digital converter; a multiplier configured to multiply an output of the first input path and the second input path; and a notch filter configured to receive an output of the multiplier, the notch filter having a stop band based on a line frequency, and a control circuit for setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a power of 2 multiple of the line frequency.

7. A power metering in accordance with claim 6 , wherein the control circuit includes a phase locked loop configured to receive one of the analog current input and the analog voltage input and to generate said sampling frequency.

8. A power metering circuit in accordance with claim 6 , wherein the control circuit comprises a frequency detector and a programmable oscillator configured to receive an output of the frequency detector and to generate said sampling frequency.

9. A power metering circuit in accordance with claim 6 , the first input path and the second input path each including a high pass filter.

10. A power metering circuit in accordance with claim 9 , wherein the first input path includes a selectable phase shifter.

11. A power metering circuit in accordance with claim 6 , including an output pulse width modulator.

12. A method, comprising: receiving an analog current input at a first analog to digital converter; receiving an analog voltage input at a second analog to digital converter; multiplying an output of the current input path and the voltage input path; notch filtering an output of the multiplier with a stop band based on a line frequency; and setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a power of 2 multiple of the line frequency.

13. A method in accordance with claim 12 , wherein setting the sampling frequency includes using a phase locked loop configured to receive one of the analog current input and the analog voltage input.

14. A method in accordance with claim 13 , wherein setting the sampling frequency comprises using a frequency detector and a programmable oscillator configured to receive an output of the frequency detector.

15. A method in accordance with claim 12 , the current input path and the voltage input path each including a highpass filter.

16. A method in accordance with claim 15 , wherein the voltage input path includes a selectable phase shifter.

17. A method in accordance with claim 12 , further comprising detecting the line frequency with a detector frequency detector comprising a low pass filter followed by a zero-crossing detector and frequency counter.

18. A power metering circuit in accordance with claim 6 , further comprising a detector frequency detector comprising a low pass filter followed by a zero-crossing detector and frequency counter.

Assignees

• Microchip Tech Inc

Inventors

• Quiquempoix Vincent
• Brumann Michael

Classifications

• G01R23/165

  using filters · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• G01R21/06 Primary

  by measuring current and voltage (G01R21/08 - G01R21/133 take precedence) · CPC title

• H03M1/36

  simultaneously only, i.e. parallel type · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title