Method of operating a finite impulse response filter

Patent metadata

Field	Value
Publication number	US-10193532-B2
Application number	US-201515310666-A
Country	US
Kind code	B2
Filing date	Jun 10, 2015
Priority date	Jun 10, 2014
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

According to one aspect of the invention, there is provided a method of operating a finite impulse response filter comprising an input; an output; and a plurality of storage elements, each coupled to the input via a sample switch and to the output via a transfer switch, the method comprising: during charging of the plurality of storage elements, applying a sample clock signal to each of the sample switches that achieves an operation mode where up to every one of the sample switches is simultaneously closed to connect all of the plurality of storage elements to the input; and during averaging of the plurality of storage elements, applying a transfer clock signal to each of the transfer switches to close one or more of the transfer switches to connect the storage elements, having charge stored therein, to the output.

First claim

The invention claimed is:

1. A method of operating a finite impulse response filter comprising an input; an output; and a plurality of storage elements each coupled to the input via a sample switch and to the output via a transfer switch, the method comprising:
during charging of the plurality of storage elements, applying a sample clock signal to each of the sample switches that achieves an operation mode where up to every one of the sample switches is simultaneously closed to connect all of the plurality of storage elements to the input; and
during averaging of the plurality of storage elements, applying a transfer clock signal to each of the transfer switches to close one or more of the transfer switches to connect the storage elements, having charge stored therein, to the output, wherein all the transfer switches are simultaneously closed during the averaging of the plurality of storage elements.

2. The method of claim 1 , wherein the total number of sample switches that are closed is determined by a filter order requirement of the finite impulse response filter.

3. The method of claim 1 , wherein the operation mode of having up to every one of the sample switches simultaneously closed is arrived at by progressively closing each of the sample switches.

4. The method of claim 3 , wherein each of the sample switches is progressively closed after a preceding sample switch has been closed for at least one period of the sample clock signal applied to the preceding sample switch.

5. The method of claim 1 , wherein the operation mode comprises the simultaneous closure of all of the sample switches.

6. The method of claim 1 , wherein the sample clock signals are in phase.

7. The method of claim 1 , wherein the finite impulse response filter further comprises a reset switch coupling each of the plurality of storage elements to ground, wherein the method further comprises:
during resetting of the plurality of storage elements, applying a reset clock signal to each of the reset switches to close the reset switches to connect the plurality of storage elements to the ground.

8. The method of claim 1 , wherein the sample clock signals are generated by the same oscillator.

9. A system comprising:
a finite impulse response filter comprising:
an input;
an output; and
a plurality of storage elements, each coupled to the input via a sample switch and to the output via a transfer switch; and

a timing circuit configured to, during charging of the plurality of storage elements, apply a sample clock signal to each of the sample switches that achieves an operation mode where up to every one of the sample switches is simultaneously closed to connect all of the plurality of storage elements to the input; wherein the timing circuit is further configured to, during averaging of the plurality of storage elements, apply a transfer clock signal to each of the transfer switches to close one or more of the transfer switches to connect the storage elements, having charge stored therein, to the output, and wherein the timing circuit is configured to simultaneously close all the transfer switches during the averaging of the plurality of storage elements.

10. The system of claim 9 , wherein the total number of sample switches, configured by the timing circuit to close, is determined by a filter order requirement of the finite impulse response filter.

11. The system of claim 9 , wherein the timing circuit is configured to arrive at the operation mode of the simultaneous closure of up to every one of the sample switches through progressive closure of each of the sample switches.

12. The system of claim 11 , wherein the timing circuit is configured to progressively close each of the sample switches after a preceding sample switch has been closed for at least one period of the sample clock signal applied to the preceding sample switch.

13. The system of claim 9 , wherein the operation mode comprises the simultaneous closure of all of the sample switches.

14. The system of claim 9 , wherein the timing circuit is configured to provide the sample clock signals in phase.

15. The system of claim 9 , wherein the finite impulse response filter further comprises a reset switch coupling each of the plurality of storage elements to ground, wherein the timing circuit is further configured to, during reset of the plurality of storage elements, apply a reset clock signal to each of the reset switches to close the reset switches to connect the plurality of storage elements to the ground.

16. The system of claim 9 , wherein the sample clock signals are generated by the same oscillator of the timing circuit.

17. A method of operating a finite impulse response filter that includes an input, an output, and a plurality of storage elements each coupled to the input via a sample switch and to the output via a transfer switch, the method comprising:
applying, during charging of the plurality of storage elements, sample clock signals that progressively close each of the sample switches after a preceding sample switch has been closed for at least one period of a sample clock signal applied to the preceding sample switch in order to achieve an operating mode where up to every one of the sample switches is simultaneously closed to connect all the plurality of storage elements to the input, wherein the preceding sample switch accumulates charge for a consecutive second period while another one of the sample switches is accumulating charge over a first period of the sample clock signal; and
applying, during averaging of the plurality of storage elements, a transfer clock signal to each of the transfer switches to close one or more of the transfer switches to connect the storage elements, having charge stored therein, to the output.

18. The method of claim 17 , wherein all the transfer switches are simultaneously closed during the averaging of the plurality of storage elements.

Assignees

• Agency Science Tech & Res

Inventors

• Choi Jaeyoung

Classifications

• H03H17/06

  Non-recursive filters · CPC title

• G06F17/10

  Complex mathematical operations {(function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544)} · CPC title

• H03H15/023 Primary

  with parallel-input configuration · CPC title

• H03H17/0223 Primary

  Computation saving measures; Accelerating measures (computations per se G06F) · CPC title