Thin film transfer, manufacturing method thereof, array substrate and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10192993-B2
Application number	US-201715704588-A
Country	US
Kind code	B2
Filing date	Sep 14, 2017
Priority date	Jan 3, 2017
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

The present disclosure provides a TFT, a manufacturing method thereof, an array substrate and a manufacturing method thereof. The TFT includes a substrate, a p-Si active layer arranged on the substrate, and a first a-Si layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate. An orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate.

First claim

What is claimed is:

1. A thin film transistor (TFT), comprising a substrate, a poly-silicon (p-Si) active layer arranged on the substrate, a first amorphous silicon (a-Si) layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate, and a buffer layer arranged on a surface of the substrate at a side adjacent to the first a-Si layer, wherein an orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate, a groove is formed in the buffer layer, and the first a-Si layer is arranged in the groove.

2. The TFT according to claim 1 , wherein the first a-Si layer has a thickness within the range of 500 to 2000 Å, and the p-Si active layer has a thickness within the range of 500 to 2000 Å.

3. The TFT according to claim 1 , further comprising a gate insulation layer, a gate electrode, an inter-layer insulation layer, a source electrode and a drain electrode arranged sequentially on the p-Si active layer away from the substrate, wherein the source electrode and the drain electrode are in contact with the p-Si active layer through via-holes in the inter-layer insulation layer and the gate insulation layer.

4. The ITT according to claim 3 , wherein the gate insulation layer is made of a material identical to the inter-layer insulation layer.

5. The TFT according to claim 1 , wherein the orthogonal projection of the p-Si active onto the substrate completely overlaps the orthogonal projection of the first a-Si layer onto the substrate.

6. An array substrate, comprising the thin film transistor (TFT) according to claim 1 .

7. The array substrate according to claim 6 , further comprising a pixel electrode electrically connected to a drain electrode of the TFT.

8. The array substrate according to claim 7 , further comprising a common electrode arranged at a layer identical to, and spaced apart from, the pixel electrode, wherein each of the pixel electrode and the common electrode is a strip-like electrode.

9. The array substrate according to claim 7 , further comprising a common electrode arranged at a layer different from the pixel electrode, wherein an upper one of the pixel electrode and the common electrode is a strip-like electrode, and a lower one of the pixel electrode and the common electrode is a plate-like electrode.

10. The array substrate according to claim 6 , further comprising a color filter layer.

11. A method for manufacturing a thin film transistor (TFT), comprising a step of forming a poly-silicon (p-Si) active layer on a substrate through crystallization, wherein prior to the step of forming the p-Si active layer, the method further comprises forming a first amorphous silicon (a-Si) layer in contact with the p-Si active layer, wherein an orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate; and
the method further comprises forming a buffer layer on a surface of the substrate at a side adjacent to the first a-Si layer, wherein a groove is formed in the buffer layer, and the first a-Si layer is arranged in the groove.

12. The method according to claim 11 , wherein the step of forming the buffer layer and the first a-Si layer comprises:
forming a buffer layer film on the substrate and forming a first photoresist layer on the buffer layer film;
exposing and developing the first photoresist layer with a first mask plate to expose a portion of the buffer layer film corresponding to the p-Si active layer;
etching the buffer layer film through an etching process, to form the buffer layer with the groove;
removing the remaining portion of the first photoresist layer;
forming a first a-Si film on the buffer layer and forming a second photoresist layer on the first a-Si film;
exposing and developing the second photoresist layer with a second mask plate, to maintain a portion of the second photoresist layer above the groove;
etching the first a-Si film and the buffer layer through an etching process, until an upper surface of the first a-Si layer in the groove is flush with a surface of the buffer layer at a position other than a position where the groove is formed; and
removing the remaining portion of the second photoresist layer.

13. The method according to claim 12 , wherein the first mask plate is identical to the second mask plate, and the first photoresist layer is made of a positive photoresist and the second photoresist layer is made of a negative photoresist, or the first photoresist layer is made of a negative photoresist and the second photoresist layer is made of a positive photoresist.

14. The method according to claim 12 , wherein the step of forming the p-Si active layer comprises:
forming a second film on the substrate with the first a-Si layer;
subjecting the second a-Si film to crystallization, to form a p-Si film;
forming a third photoresist layer on the p-Si film, and exposing and developing the third photoresist layer with the second mask plate;
etching the p-Si film through an etching process to form the p-Si active layer; and
removing the remaining portion of the third photoresist layer, or
the step of forming the p-Si active layer comprises:
forming a second a-Si film on the substrate with the first a-Si layer;
forming a third photoresist layer on the second a-Si film;
exposing and developing the third photoresist layer with the second mask plate;
etching the second a-Si film through an etching process to form a second a-Si layer;
removing the remaining portion of the third photoresist layer; and
subjecting the second a-Si layer to crystallization, to form the p-Si active layer.

15. The method according to claim 12 , wherein the etching process is a dry-etching process.

16. The method according to claim 11 , wherein the first a-Si layer has a thickness within the range of 500 to 2000 Å, and the p-Si active layer has a thickness within the range of 500 to 2000 Å.

17. The method according to claim 11 , wherein the orthogonal projection of the p-Si active layer onto the substrate completely overlaps the orthogonal projection of the first a-Si layer onto the substrate.

18. A method for manufacturing an array substrate, comprising the method according to claim 11 .

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Ren Yanwei
• Sun Chaochao
• Zhang Kunpeng
• Fang Yezhou
• Xu Jingyi

Classifications

• H01L27/3272

  Electricity · mapped topic

• G02F2202/103

  a-Si · CPC title

• G03F7/30

  Imagewise removal using liquid means · CPC title

• G02F2202/104

  poly-Si · CPC title

• G02F1/134363

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title