Semiconductor ferroelectric storage transistor and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-10192972-B2
Application number	US-201715690054-A
Country	US
Kind code	B2
Filing date	Aug 29, 2017
Priority date	Jun 5, 2012
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body ( 11 ) and a gate electrode conductor ( 4 ) are sequentially laminated in this order on a semiconductor base ( 10 ) that has a source region ( 12 ) and a drain region ( 13 ). The insulating body ( 11 ) is configured by laminating a first insulating body ( 1 ) and a second insulating body ( 2 ) in this order on the base ( 10 ), and the second insulating body ( 2 ) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.

First claim

The invention claimed is:

1. A semiconductor ferroelectric memory transistor comprising a semiconductor body which has a source region and a drain region on which an insulator and a gate electrode conductor are stacked in that order,
wherein the insulator includes a ferroelectric insulator comprising an oxide of strontium, calcium, bismuth, and tantalum, and the oxide of strontium, calcium, bismuth, and tantalum is represented by Sr-Ca-Bi-Ta-O, and
wherein in the Sr-Ca-Bi-Ta-O, a ratio of the calcium element to the strontium element is larger than 0 and not more than two-thirds.

2. The semiconductor ferroelectric memory transistor according to claim 1 ,
wherein the insulator is comprised of a first insulator and a second insulator stacked on the body in that order, and
wherein the second insulator is the ferroelectric insulator comprising an oxide of strontium, calcium, bismuth, and tantalum, and the oxide of strontium, calcium, bismuth represented by the Sr-Ca-Bi-Ta-O.

3. The semiconductor ferroelectric memory transistor according to claim 2 , wherein the oxide of strontium, calcium, bismuth, and tantalum, which is Sr-Ca-Bi-Ta-O has a bismuth layered perovskite-type crystal structure.

4. The semiconductor ferroelectric memory transistor according to claim 3 , wherein the insulator has a film thickness of 250 nm or less.

5. The semiconductor ferroelectric memory transistor according to claim 3 , wherein the first insulator has a film thickness of 15 nm or less.

6. The semiconductor ferroelectric memory transistor according to claim 2 , wherein the first insulator is an oxide of hafnium, an oxide of hafnium and aluminum, an oxide which includes hafnium, an oxide of strontium and titanium, a composite oxide of two or more of any of these, or an oxide layer stack of two or more of any of these.

7. The semiconductor ferroelectric memory transistor according to claim 6 , wherein the insulator has a film thickness of 250 nm or less.

8. The semiconductor ferroelectric memory transistor according to claim 6 , wherein the first insulator has a film thickness of 15 nm or less.

9. The semiconductor ferroelectric memory transistor according to claim 2 , wherein the insulator has a film thickness of 250 nm or less.

10. The semiconductor ferroelectric memory transistor according to claim 2 , wherein the first insulator has a film thickness of 15 nm or less.

11. The semiconductor ferroelectric memory transistor according to claim 1 , wherein the oxide of strontium, calcium, bismuth, and tantalum, which is Sr-Ca-Bi-Ta-O, has a bismuth layered perovskite-type crystal structure.

12. The semiconductor ferroelectric memory transistor according to claim 11 , wherein the insulator has a film thickness of 250 nm or less.

13. The semiconductor ferroelectric memory transistor according to claim 1 , wherein the insulator has a film thickness of 250 nm or less.

14. A method of producing a semiconductor ferroelectric memory transistor according to claim 1 , the method comprising:
cleaning a semiconductor body surface;
depositing an insulator;
forming a gate electrode conductor; and
providing a heat treatment;
wherein the semiconductor ferroelectric memory transistor includes the semiconductor body having a source region and a drain region on which the insulator including the ferroelectric insulator comprising an oxide of strontium, calcium, bismuth, and tantalum represented by the Sr-Ca-Bi-Ta-O and a gate electrode conductor are stacked in that order.

15. The method according to claim 14 , wherein the heat treatment has a temperature of 760° C. to 833° C.

16. The method according to claim 14 , wherein the insulator deposition step includes depositing the ferroelectric insulator comprised of an oxide of strontium, calcium, bismuth, and tantalum represented by the Sr-Ca-Bi-Ta-O via pulse laser deposition or sputtering using a plurality of oxide targets with different ratios of composition of strontium, calcium, bismuth, and tantalum.

17. A semiconductor ferroelectric memory transistor comprising a semiconductor body which has a source region and a drain region on which an insulator and a gate electrode conductor are stacked in that order, wherein
the insulator comprises a ferroelectric insulator comprising an oxide of strontium, calcium, bismuth, and tantalum, and the oxide of strontium, calcium, bismuth, and tantalum is represented by Sr-Ca-Bi-Ta-O.

18. The semiconductor ferroelectric memory transistor according to claim 17 , wherein a ratio of the calcium element to the strontium element in the Sr-Ca-Bi-Ta-O is larger than 0 and not more than two-thirds.

19. The semiconductor ferroelectric memory transistor according to claim 18 , wherein the Sr-Ca-Bi-Ta-O has a bismuth layered perovskite-type crystal structure.

20. The semiconductor ferroelectric memory transistor according to claim 19 , wherein the insulator has a film thickness of 250 nm or less.

21. The semiconductor ferroelectric memory transistor according to claim 19 , wherein the first insulator has a film thickness of 15 nm or less.

22. The semiconductor ferroelectric memory transistor according to claim 18 , wherein the first insulator is an oxide of halfnium, an oxide of halfnium and aluminum, an oxide which includes halfnium, an oxide of strontium and titanium, a composite oxide of two or more of any of these, or an oxide layer stack of two or more of any of these.

23. The semiconductor ferroelectric memory transistor according to claim 18 , wherein the insulator has a film thickness of 250 nm or less.

24. The semiconductor ferroelectric memory transistor according to claim 18 , wherein the first insulator has a film thickness of 15 nm or less.

25. The semiconductor ferroelectric memory transistor according to claim 17 ,
wherein the insulator is comprised of a first insulator and a second insulator stacked on the body in that order, and
wherein the second insulator is the ferroelectric insulator comprising an oxide of strontium, calcium, bismuth, and tantalum, and the oxide of strontium, calcium, bismuth represented by the Sr-Ca-Bi-Ta-O.

26. The semiconductor ferroelectric memory transistor according to claim 25 , wherein the insulator has a film thickness of 250 nm or less.

27. The semiconductor ferroelectric memory transistor according to claim 17 , wherein the Sr-Ca-Bi-Ta-O has a bismuth layered perovskite-type crystal structure.

28. The semiconductor ferroelectric memory transistor according to claim 27 , wherein the insulator has a film thickness of 250 nm or less.

29. The semiconductor ferroelectric memory transistor according to claim 27 , wherein the first insulator has a film thickness of 15 nm or less.

30. The semiconductor ferroelectric memory transistor according to claim 17 , wherein the insulator has a film thickness of 250 nm or less.

31. A method of producing a semiconductor ferroelectric memory transistor, the method comprising:
cleaning a semiconductor body surface;
depositing an insulator;
forming a gate electrode conductor; and
providing a heat treatment, wherein
the semiconductor ferroelectric memory transistor comprises the semiconductor body having a source region and a drain region on which the insulator including a ferroelectric insulator comprising an oxide of strontium, calcium, bismuth, and tantalum represented by Sr-Ca

Assignees

• Aist

Inventors

• Sakai Shigeki
• Zhang Wei
• Takahashi Mitsue

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/69398 Primary

  the material having a perovskite structure, e.g. BaTiO3 · CPC title

• H10P14/6329

  using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title