Thin film transistor and method of manufacturing the same, array substrate and display panel

Patent metadata

Field	Value
Publication number	US-10192894-B2
Application number	US-201615143810-A
Country	US
Kind code	B2
Filing date	May 2, 2016
Priority date	Aug 19, 2015
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

Embodiments of the present application provide a thin film transistor and a method of manufacturing the same, an array substrate and a display panel. The thin film transistor comprises, successively from the bottom up, a gate, a first common electrode located in the same layer as the gate, a gate insulating layer, an active layer, a pixel electrode, a source-drain electrode layer and a passivation layer located above the layer where the gate is located, and a second common electrode located on the passivation layer, and the thin film transistor further comprises at least one connection electrode located in a same layer as the pixel electrode, wherein at least two via holes are provided between the first common electrode and the second common electrode so as to connect the first common electrode and the second common electrode through the connection electrode.

First claim

What is claimed is:

1. A thin film transistor comprising, successively from the bottom up, a gate, a first common electrode located in a same layer as the gate, a gate insulating layer, an active layer, a pixel electrode, a source-drain electrode layer and a passivation layer located above the layer where the gate is located, and a second common electrode located on the passivation layer, wherein,
the thin film transistor further comprises at least one connection electrode located in a same layer as the pixel electrode, wherein at least two via holes are provided between the first common electrode and the second common electrode so as to connect the first common electrode and the second common electrode through the connection electrode.

2. The thin film transistor according to claim 1 , wherein the connection electrode is provided between two adjacent ones of the at least two via holes.

3. The thin film transistor according to claim 2 , wherein the at least two via holes comprises a first via hole provided in the gate insulating layer and a second via hole provided in the passivation layer, and wherein the first common electrode is connected with the connection electrode through the first via hole, and the connection electrode is connected with the second common electrode through the second via hole.

4. The thin film transistor according to claim 3 , wherein the thin film transistor further comprise at least one third common electrode located in a same layer as the source-drain electrode layer, wherein each third common electrode is connected with a corresponding connection electrode, and the third common electrode is connected with the second common electrode through the second via hole.

5. The thin film transistor according to claim 3 , wherein the first via hole has a depth equal to the thickness of the gate insulating layer, and the second via hole has a depth equal to the thickness of the passivation layer.

6. The thin film transistor according to claim 2 , wherein the thin film transistor further comprise at least one third common electrode located in a same layer as the source-drain electrode layer, wherein each third common electrode is connected with a corresponding connection electrode.

7. The thin film transistor according to claim 1 , wherein the connection electrode is a transparent conductive layer.

8. An array substrate, comprising the thin film transistor according to claim 1 .

9. The array substrate according to claim 8 , wherein the connection electrode is provided between two adjacent ones of the at least two via holes.

10. The array substrate according to claim 9 , wherein the at least two via holes comprises a first via hole provided in the gate insulating layer and a second via hole provided in the passivation layer, and wherein the first common electrode is connected with the connection electrode through the first via hole, and the connection electrode is connected with the second common electrode through the second via hole.

11. The array substrate according to claim 10 , wherein the thin film transistor further comprise at least one third common electrode located in a same layer as the source-drain electrode layer, wherein each third common electrode is connected with a corresponding connection electrode, and the third common electrode is connected with the second common electrode through the second via hole.

12. The array substrate according to claim 10 , wherein the first via hole has a depth equal to the thickness of the gate insulating layer, and the second via hole having a depth equal to the thickness of the passivation layer.

13. The array substrate according to claim 9 , wherein the thin film transistor further comprise at least one third common electrode located in a same layer as the source-drain electrode layer, wherein each third common electrode is connected with a corresponding connection electrode.

14. The array substrate according to claim 8 , wherein the connection electrode is a transparent conductive layer.

15. A display panel, comprising the array substrate according to claim 8 .

16. A method of manufacturing the thin film transistor according to claim 1 , comprising forming the gate, the first common electrode and the gate insulating layer successively on a base substrate, wherein the gate is located in a same layer as the first common electrode, and the method further comprises:
forming the active layer on the gate insulating layer, and forming a first via hole in a portion of the gate insulating layer located on the first common electrode;
forming the pixel electrode after forming the active layer, and forming the connection electrode at the first via hole such that the connection electrode is connected with the first common electrode through the first via hole;
forming a drain electrode and a source electrode corresponding to the active layer;
forming the passivation layer, and forming a second via hole in a portion of the passivation layer located on the connection electrode;
forming the second common electrode on the passivation layer such that the second common electrode is connected with the connection electrode through the second via hole.

17. The method according to claim 16 , wherein forming the active layer on the gate insulating layer, and forming the first via hole in the portion of the gate insulating layer located on the first common electrode comprise:
etching the portion of the gate insulating layer located on the first common electrode so as to form the first via hole, and forming the active layer on the gate insulating layer through exposure by using a mask; or
forming the active layer on the gate insulating layer through exposure by using a mask, and etching the portion of the gate insulating layer located on the first common electrode so as to form the first via hole.

18. A method of manufacturing the thin film transistor according to claim 1 , comprising forming the gate, the first common electrode and the gate insulating layer successively on a base substrate, wherein the gate is located in a same layer as the first common electrode, and the method further comprises:
forming the active layer on the gate insulating layer, and forming a first via hole in a portion of the gate insulating layer located on the first common electrode;
forming the pixel electrode after forming the active layer, and forming the connection electrode at the first via hole such that the connection electrode is connected with the first common electrode through the first via hole;
forming a drain electrode, a source electrode and a third common electrode at the same time such that the third common electrode is connected with the connection electrode;
forming the passivation layer, and forming a second via hole in a portion of the passivation layer located on the third common electrode;
forming the second common electrode on the passivation layer such that the second common electrode is connected with the third common electrode through the second via hole.

19. The method according to claim 18 , wherein forming the active layer on the gate insulating layer, and forming the first via hole in the portion of the gate insulating layer located on the first common electrode comprise:
etching the portion of the gate insulating layer located on the first common electrode so as to form the first via hole, and forming the active layer on the gate insulating layer through exposure by using a mask; or
forming the active layer on the gate insulating layer through exposure by using a mask, and etching the por

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Jiang Tao
• Han Junhao
• Song Botao
• Lin Liang

Classifications

• H01L27/1248

  Electricity · mapped topic

• H01L27/124 Primary

  Electricity · mapped topic

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title