Display device and data driver

Patent metadata

Field	Value
Publication number	US-10192515-B2
Application number	US-201615384558-A
Country	US
Kind code	B2
Filing date	Dec 20, 2016
Priority date	Jul 22, 2016
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

A data driver for a display device comprises a first boost circuit, a first gate clock generation circuit, a first level shift circuit, and a data drive circuit. The first boost circuit is used to receive a supply voltage value and generate at least one preset voltage value. The first gate clock generation circuit is electrically coupled to the first boost circuit, and is used to receive a plurality of timing signals and at least one preset voltage value, and generate at least one first timing signal. The first level shift circuit is used to receive the at least one first timing signal and generate at least one gate timing signal. The data drive circuit is used to receive the timing signals, and generate a plurality of display data signals.

First claim

What is claimed is:

1. A data driver applicable to a display device, comprising:
a first boost circuit, receiving a supply voltage value and generating a first boosted voltage at a first preset voltage value;
a first gate clock generation circuit, electrically coupled to the first boost circuit, receiving a plurality of timing signals and the first boosted voltage, and generating a first timing signal;
a first level shift circuit, receiving a first timing signal and generating a first gate timing signal; and
a data drive circuit, receiving the plurality of timing signals and generating a plurality of display data signals;
wherein the first boost circuit is electrically coupled to a second boost circuit of a second data driver, and the second booster circuit generates a second boosted voltage at the first preset voltage value.

2. The data driver according to claim 1 , wherein the first boost circuit outputs to the second boost circuit, and the second boost circuit outputs to the first boost circuit.

3. A data driver applicable to a display device, comprising:
a first boost circuit, receiving a supply voltage value and generating a first boosted voltage at a first preset voltage value;
a first gate clock generation circuit, electrically coupled to the first boost circuit, receiving a plurality of timing signals and the first boosted voltage, and generating a first timing signal;
a first level shift circuit, receiving a first timing signal and generating a first gate timing signal; and
a data drive circuit, receiving the plurality of timing signals and generating a plurality of display data signals;
wherein the first gate clock generation circuit generates a second timing signal; and
wherein the data driver comprises a second level shift circuit, receiving the second timing signal and generating a second gate timing signal, wherein the first level shift circuit is on a first side of the data driver, the second level shift circuit is on a second side of the data driver, and the first side is opposite to the second side.

4. A display device, comprising:
a power supply circuit, for providing a supply voltage value;
a timing controller, for providing a plurality of timing signals;
a first data driver, electrically coupled to the timing controller and the power supply circuit, receiving the plurality of timing signals and the supply voltage value, and generating a plurality of display data signals and a plurality of first gateway timing signals, wherein the first data driver comprises a first boost circuit receiving the supply voltage value and generating a first boosted voltage at a first preset voltage value;
a gate driver, electrically coupled to the first data driver, receiving the first gateway timing signals, and generating a plurality of gate driving signals; and
a plurality of pixel units, electrically coupled to the first data driver and the gate driver, receiving the display data signals according to the gate driving signals;
wherein the first boost circuit is electrically coupled to a second boost circuit of a second data driver, and the second booster circuit generates a second boosted voltage at the first preset voltage value.

5. The display device according to claim 4 , wherein the first data driver further comprises:
a first gate clock generation circuit, electrically coupled to the first boost circuit, receiving the plurality of timing signals and the first boosted voltage, and generating a first timing signal;
a first level shift circuit, receiving the first timing signal and generating a first gateway timing signal; and
a data drive circuit, receiving the plurality of timing signals and generating the display data signals.

6. The display device according to claim 5 , wherein the first gate clock generation circuit generates a second timing signal.

7. The display device according to claim 6 , wherein the first data driver comprises a second level shift circuit, receiving the second timing signal and generating a second gate timing signal, wherein the first level shift circuit is on a first side of the first data driver, the second level shift circuit is on a second side of the first data driver, and the first side is opposite to the second side.

8. The display device according to claim 4 , wherein the first boost circuit outputs to the second boost circuit, and the second boost circuit outputs to the first boost circuit.

9. The display device according to claim 4 , wherein the power supply circuit and the timing controller are on a printed circuit board.

Assignees

• Au Optronics Corp

Inventors

• Su Shih-Yuan
• Siao Kai-Yuan
• Li Jian-Feng
• Wen Chun-Kuei

Classifications

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/0221

  with use of split matrices (G09G3/3644 and G09G3/3666 take precedence) · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G5/003 Primary

  Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092) · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title