Memory system

Patent metadata

Field	Value
Publication number	US-10191664-B2
Application number	US-201615294255-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	Oct 16, 2015
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

First claim

What is claimed is:

1. A memory system comprising:
a first memory device including a first memory and a first memory controller configured to control the first memory to store data;
a second memory device including a second memory and a second memory controller configured to control the second memory to store data; and
a processor is configured to execute an operating system (OS) and an application to access a data storage memory through the first and second memory devices,
wherein the first and second memories are separated from the processor,
wherein the second memory controller transfers a signal between the processor and the second memory device based on at least one of values of a handshaking information field included in the signal,
wherein the first memory includes a plurality of first high-capacity memory cores configured to work as cache memories for the second memory,
wherein the first memory device further includes a first memory management logic operatively and commonly coupled with the plurality of first high-capacity memory cores, and configured to support high-speed data communication between the processor and the plurality of first high-capacity memory cores,
wherein the second memory includes a plurality of second high-capacity memory cores configured to work as system memories,
wherein the second memory device further includes a second memory management logic operatively and commonly coupled with the plurality of second high-capacity memory cores, and configured to support data communication between the processor and the plurality of second high-capacity memory cores,
wherein the second memory management logic includes a buffer configured to buffer write data, based on which the plurality of second memory cores are updated,
wherein the second memory controller firstly buffers the write data in the buffer, and then the second memory management logic independently updates the plurality of second memory cores based on the buffered write data, and
wherein the at least one of values of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

2. The memory system of claim 1 , wherein the second memory controller includes:
a handshaking interface configured to transfer the signal between the second memory device and the processor; and
a register configured to temporarily store data read out from the second memory.

3. The memory system of claim 1 , wherein the data request signal includes a command and an address for the second memory device.

4. The memory system of claim 1 ,
wherein the second memory controller includes a storage unit, and
wherein the second memory controller reads data from the second memory and temporarily stores the read data in the storage unit in response to the data request signal.

5. The memory system of claim 4 , wherein the second memory controller provides the data ready signal to the processor when the second memory controller temporarily stores the read data in the storage unit in response to the data request signal.

6. The memory system of claim 5 , wherein the processor provides the session start signal to receive the read data temporarily stored in the storage unit in response to the data ready signal.

7. The memory system of claim 1 , wherein the first memory device is a volatile memory device.

8. The memory system of claim 1 , wherein the second memory device is a nonvolatile memory device.

9. The memory system of claim 8 , wherein the nonvolatile memory device is a nonvolatile random access memory device.

10. A memory system comprising:
a first memory device including a first memory and a first memory controller configured to control the first memory to store data;
a second memory device including a second memory and a second memory controller configured to control the second memory to store data; and

a processor configured to access the first and second memories, wherein the second memory controller transfers a signal between the processor and the second memory device based on at least one of values of a handshaking information field included in the signal,
wherein the first memory includes a plurality of first high-capacity memory cores configured to work as cache memories for the second memory,
wherein the first memory device further includes a first memory management logic operatively and commonly coupled with the plurality of first high-capacity memory cores, and configured to support high-speed data communication between the processor and the plurality of first high-capacity memory cores,
wherein the second memory includes a plurality of second high-capacity memory cores configured to work as system memories,

wherein the second memory device further includes a second memory management logic operatively and commonly coupled with the plurality of second high-capacity memory cores, and configured to support data communication between the processor and the plurality of second high-capacity memory cores,
wherein the second memory management logic includes a buffer configured to buffer write data, based on which the plurality of second memory cores are updated,
wherein the second memory controller firstly buffers the write data in the buffer, and then second memory management logic independently updates the plurality of second memory cores based on the buffered write data, and
wherein the at least one of values of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

11. The memory system of claim 10 , wherein the second memory controller includes:
a handshaking interface configured to transfer the signal between the second memory device and the processor; and
a register configured to temporarily store data read out from the second memory.

12. The memory system of claim 11 , wherein the data request signal includes a command and an address for the second memory device.

13. The memory system of claim 11 ,
wherein the second memory controller includes a storage unit, and
wherein the second memory controller reads data from the second memory and temporarily stores the read data in the storage unit in response to the data request signal.

14. The memory system of claim 13 , wherein the second memory controller provides the data ready signal to the processor when the second memory controller temporarily stores the read data in the storage unit in response to the data request signal.

15. The memory system of claim 14 , wherein the processor provides the session start signal to receive the read data temporarily stored in the storage unit in response to the data ready signal.

16. The memory system of claim 10 , wherein the first memory device is a volatile memory device.

17. The memory system of claim 10 , wherein the second memory device is a nonvolatile memory device.

18. The memory system of claim 17 , wherein the nonvolatile memory device is a nonvolatile random access memory device.

Assignees

• Sk Hynix Inc

Inventors

• Lee Yong-Woo
• Kim Min-Chang
• Kim Chang-Hyun
• Lee Do-Yun
• Lee Jae-Jin
• Jung Hun-Sam

Classifications

• G06F12/10

  Address translation · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F2212/1016

  Performance improvement · CPC title