Low-power Type-C receiver with high idle noise and DC-level rejection

Patent metadata

Field	Value
Publication number	US-10191524-B2
Application number	US-201715787340-A
Country	US
Kind code	B2
Filing date	Oct 18, 2017
Priority date	Jun 19, 2015
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

Techniques for low-power USB Type-C receivers with high DC-level shift tolerance are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to receive data from an incoming signal on the CC line even when the incoming signal has more than 250 mV of DC offset with respect to local ground, and to operate in presence of a VBUS charging current that is specified in a USB-PD specification.

First claim

What is claimed is:

1. A device comprising:
a receiver circuit coupled to a Configuration Channel (CC) line of a Universal Serial Bus (USB) Type-C subsystem, wherein the receiver circuit is configured to:
receive valid BMC-encoded data from an incoming signal on the CC line when the incoming signal has more than 250 mV of direct current (DC) offset with respect to a local ground; and
operate in the presence of a VBUS charging current that is specified in a USB-PD specification.

2. The device of claim 1 , wherein the receiver circuit is configured to support Type-C cables that are non-compliant with respect to DC offsets allowed in the USB-PD specification.

3. The device of claim 1 , wherein the receiver circuit is configured to cause generation of a wake-up signal based on the incoming signal when the incoming signal carries the valid BMC-encoded data.

4. The device of claim 1 , wherein the receiver circuit is configured to provide a single path for both activity wakeup on the CC line and receipt of the valid BMC-encoded data.

5. The device of claim 1 , wherein the receiver circuit comprises:
a capacitor coupled in series from the CC line to a restore node, the capacitor configured to block a DC component of the incoming signal on the CC line;
a restoration circuit coupled to the restore node and configured to shift a voltage of the incoming signal to a first reference voltage; and
a slicer circuit coupled to the restore node and configured to compare the shifted voltage to a second reference voltage.

6. The device of claim 1 , wherein the device comprises an integrated circuit (IC), wherein the IC includes the USB Type-C subsystem and the USB Type-C subsystem includes the receiver circuit.

7. An integrated circuit (IC) controller comprising:
a Universal Serial Bus (USB) Type-C subsystem; and
a receiver circuit coupled to a Configuration Channel (CC) line of the USB Type-C subsystem, the receiver circuit comprising:
a capacitor coupled in series from the CC line to a restore node, the capacitor configured to block a direct current (DC) component of an incoming signal on the CC line;
a restoration circuit coupled to the restore node and configured to shift a voltage of the incoming signal to a first reference voltage; and
a slicer circuit coupled to the restore node and configured to compare the shifted voltage to a second reference voltage;

wherein the receiver circuit is configured to operate in presence of VBUS charging currents that are specified in a USB-PD specification.

8. The IC controller of claim 7 , wherein the receiver circuit is configured to support Type-C cables that are non-compliant with respect to DC offsets allowed in the USB-PD specification.

9. The IC controller of claim 7 , wherein the receiver circuit is configured to cause generation of a wake-up signal based the incoming signal when the incoming signal carries valid BMC-encoded data.

10. The IC controller of claim 7 , wherein the receiver circuit is configured to provide a single path for both activity wakeup on the CC line and receipt of valid BMC-encoded data.

11. The IC controller of claim 7 , wherein the receiver circuit is configured to receive valid BMC-encoded data from the incoming signal on the CC line when the incoming signal has more than 250 mV of DC offset with respect to a local ground.

12. A Universal Serial Bus (USB) Type-C cable, comprising:
a first Type-C connector disposed at a first end of the Type-C cable; and
a first integrated circuit (IC) chip disposed within the Type-C cable and coupled to a Configuration Channel (CC) line of the first Type-C connector, wherein the first IC chip includes a first receiver circuit configured at least to:
receive valid BMC-encoded data from an incoming signal on the CC line when the incoming signal has more than 250 mV of direct current (DC) offset with respect to a local ground; and
operate in presence of a VBUS charging current on a VBUS line of the first Type-C connector, wherein the VBUS charging current is specified in a USB-PD specification.

13. The USB Type-C cable of claim 12 , wherein the USB Type-C cable is non-compliant with respect to DC offsets allowed in the USB-PD specification.

14. The USB Type-C cable of claim 12 , wherein the first receiver circuit is configured to cause generation of a wake-up signal based the incoming signal when the incoming signal carries the valid BMC-encoded data.

15. The USB Type-C cable of claim 12 , wherein the first receiver circuit is configured to provide a single path for both activity wakeup on the CC line and receipt of the valid BMC-encoded data.

16. The USB Type-C cable of claim 12 , wherein the first receiver circuit comprises:
a capacitor coupled in series from the CC line to a restore node, the capacitor configured to block a DC component of the incoming signal on the CC line;
a restoration circuit coupled to the restore node and configured to shift a voltage of the incoming signal to a first reference voltage; and
a slicer circuit coupled to the restore node and configured to compare the shifted voltage to a second reference voltage.

17. The USB Type-C cable of claim 12 , wherein the USB Type-C cable further comprises:
a second Type-C connector disposed at a second end of the Type-C cable and coupled to the CC line; and
a second IC chip disposed within the Type-C cable and coupled to the CC line, wherein the second IC chip includes a second receiver circuit.

18. The USB Type-C cable of claim 17 , wherein the second receiver circuit comprises:
a capacitor coupled in series from the CC line to a restore node, the capacitor configured to block a DC component of the incoming signal on the CC line;
a restoration circuit coupled to the restore node and configured to shift a voltage of the incoming signal to a first reference voltage; and
a slicer circuit coupled to the restore node and configured to compare the shifted voltage to a second reference voltage.

19. The USB Type-C cable of claim 12 , wherein the first Type-C connector is a Type-C receptacle.

20. The USB Type-C cable of claim 12 , further comprising a second USB 2.0 connector disposed at a second end of the Type-C cable.

Assignees

• Cypress Semiconductor Corp

Inventors

• Agarwal Rishi
• Bodnaruk Nicholas Alexander

Classifications

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F1/266 Primary

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H02J7/00

  Circuit arrangements for charging or discharging batteries or for supplying loads from batteries · CPC title

• G06F1/22 Primary

  Means for limiting or controlling the pin/gate ratio · CPC title