Power detection circuit

Patent metadata

Field	Value
Publication number	US-10191086-B2
Application number	US-201615079364-A
Country	US
Kind code	B2
Filing date	Mar 24, 2016
Priority date	Mar 24, 2016
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

An apparatus for detecting a change in a voltage level of a power supply is disclosed. An inverter coupled to a first power supply may generate a signal dependent upon a voltage level of a second power supply. A latch coupled to the first power supply may be set based on a first voltage level of the second power supply and a first value of the signal, and re-set based on a second voltage level of the second power supply and a second value of the signal different than the first value of the signal.

First claim

What is claimed is:

1. An apparatus, comprising:
an inverter coupled to a first power supply, wherein the inverter is configured to generate a signal dependent upon a second power supply; and
a latch configured to:
store a first value dependent upon a first voltage level of the second power supply and a first value of the signal; and
store a second value dependent upon a second voltage level of the second power supply and a second value of the signal, wherein the second value of the signal is different from the first value of the signal.

2. The apparatus of claim 1 , wherein the first voltage level of the second power supply is greater than the second voltage level of the second power supply.

3. The apparatus of claim 1 , wherein the first voltage level of the second power supply is less than the second voltage level of the second power supply.

4. The apparatus of claim 1 , wherein a third voltage level of the first power supply is greater than the first voltage level of the second power supply.

5. The apparatus of claim 1 , wherein the inverter includes a field effect transistor whose source terminal is coupled to the first power supply and whose control terminal is coupled to a storage node in the latch.

6. The apparatus of claim 1 , wherein the latch includes a first device and a second device, wherein control terminals of the first and second devices are coupled to the second power supply, and wherein the latch further includes a third and fourth devices, wherein control terminals of the third and fourth devices are coupled to the signal.

7. A method, comprising:
setting a latch circuit based on a first voltage level of a first power supply, wherein the latch circuit is coupled to a second power supply different from the first power supply;
re-setting the latch circuit based on a second voltage level of the first power supply, wherein the second voltage level of the first power supply is different than the first voltage level of the first power supply; and
disabling input to a circuit block that includes the latch circuit, in response to re-setting the latch circuit based on the second voltage level of the first power supply.

8. The method of claim 7 , wherein the first voltage level of the first power supply is greater than the second voltage level of the first power supply.

9. The method of claim 7 , wherein the first voltage level of the first power supply is less than the second voltage level of the first power supply.

10. The method of claim 7 , further comprising signaling a reset condition to a computing system in response to re-setting the latch circuit based on the second voltage level of the first power supply.

11. The method of claim 7 , further comprising disabling a computing system in response to re-setting the latch circuit based on the second voltage level of the first power supply.

12. A system, comprising:
a first circuit block coupled to a first power supply; and
a second circuit block coupled to the first circuit block and a second power supply, wherein the second circuit block includes a power detection circuit configured to:
set a latch based on a first voltage level of the first power supply;
re-set the latch based on a second voltage level of the first power supply, wherein the second voltage level of the first power supply is different than the first voltage level of the first power supply; and
disable at least one input to the second circuit block, in response to re-setting the latch.

13. The system of claim 12 , wherein the first voltage level of the first power supply is greater than the second voltage level of the first power supply.

14. The system of claim 12 , wherein the first voltage level of the first power supply is less than the second voltage level of the first power supply.

15. The system of claim 12 , wherein the power detection circuit is further configured to signal a reset condition to the system in response to re-setting the latch.

16. The system of claim 12 , wherein the power detection circuit is further configured to disable the system in response to re-setting the latch.

Assignees

• Apple Inc

Inventors

• Seningen Michael R
• Wang Zhao
• Bhatia Ajay

Classifications

• G01R15/09 Primary

  Autoranging circuits · CPC title

• G01R31/40

  Testing power supplies (testing photovoltaic devices H02S50/10) · CPC title