Paralleling mechanical relays for increased current carrying and switching capacity

US10186857B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10186857-B2
Application numberUS-201615155795-A
CountryUS
Kind codeB2
Filing dateMay 16, 2016
Priority dateMay 16, 2016
Publication dateJan 22, 2019
Grant dateJan 22, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Multiple relays are connected in parallel by including one or more semiconductor devices connected across the relay contacts. The semiconductor devices are triggered to conduct and shunt transient currents during the opening and closing of the relay contacts to protect the relay contacts from overcurrent and to eliminate arcing during relay switching. This permits a combination of smaller relays to replace a larger and more expensive relay in applications that require switching of large load currents.

First claim

Opening claim text (preview).

What is claimed: 1. A relay system for switching current to a load comprising: a plurality of relays arranged in an electrically parallel configuration, each relay sized to carry a portion of the current to the load; and a semiconductor switch assembly connected across the plurality of relays configured to in a first mode, activate the semiconductor switch assembly before the plurality of relays such that an amount current sufficient to prevent arcing in the plurality of relays passes through the semiconductor switch assembly by virtue of a low on-resistance of the semiconductor switch assembly relative to a resistance of the relays, and in a second mode, activate the semiconductor switch assembly as the current across the plurality of relays increases such that the current is shunted through the semiconductor switch assembly until the plurality of relays are fully open. 2. The relay system of claim 1 , wherein said semiconductor switch assembly comprises one or more silicon-controlled rectifiers. 3. The relay system of claim 1 , wherein said semiconductor switch assembly comprises one or more field effect transistors. 4. The relay system of claim 1 , wherein the semiconductor switch comprises one or more insulated gate bipolar transistors. 5. The relay system of claim 1 , wherein said semiconductor switch assembly comprises one or more bipolar junction transistors. 6. The relay system of claim 2 , further comprising drive circuitry for providing gate trigger voltages to turn on the one or more silicon-controlled rectifiers. 7. The relay system of claim 6 , wherein the drive circuitry includes a bilateral switch. 8. The relay system of claim 7 , wherein the bilateral switch is light activated. 9. The relay system of claim 8 , wherein the bilateral switch is triac. 10. The relay system of claim 7 , wherein the bilateral switch provides optical isolation. 11. A virtual circuit breaker comprising: a plurality of relays arranged in an electrically parallel configuration, each relay sized to carry a portion of current to a load; a semiconductor switch assembly connected across the plurality of relays; a control circuit for monitoring current to said load and opening said relay contacts when an over current or short circuit condition is sensed; and wherein the semiconductor switch assembly is configured to, in a first mode, activate the semiconductor switch assembly before the plurality of relays such that an amount current sufficient to prevent arcing in the plurality of relays passes through the semiconductor switch assembly by virtue of a low on-resistance of the semiconductor switch assembly relative to a resistance of the relays, and in a second mode, activate the semiconductor switch assembly as the current across the plurality of relays increases such that the current is shunted through the semiconductor switch assembly until the plurality of relays are fully open. 12. The virtual circuit breaker of claim 11 , wherein said semiconductor switch assembly is configured to shunt excess current away from each of the plurality of relays during said transient time period. 13. The virtual circuit breaker of claim 12 , wherein said semiconductor switch assembly comprises one or more silicon-controlled rectifiers that are triggered on to shunt said excess current during said transient time period. 14. A method for reducing contact failure when a plurality of relays, each having one or more contacts, are arranged in an electrically parallel configuration to switch current to a load, comprising the steps of: connecting a semiconductor switch assembly across said plurality of relays, and in a first mode, activating the semiconductor switch assembly before the plurality of relays such that an amount current sufficient to prevent arcing in the plurality of relays passes through the semiconductor switch assembly by virtue of a low on-resistance of the semiconductor switch assembly relative to a resistance of the relays; and in a second mode, activating the semiconductor switch assembly as the current across the plurality of relays increases such that the current is shunted through the semiconductor switch assembly until the plurality of relays are fully open.

Assignees

Inventors

Classifications

  • Multiple main contacts for the purpose of dividing the current through, or potential drop along, the arc · CPC title

  • the static switching means being an insulated gate bipolar transistor, e.g. IGBT, Darlington configuration of FET and bipolar transistor · CPC title

  • Contacts shunted by static switch means · CPC title

  • H02H9/02Primary

    responsive to excess current {(current limitation for voltage regulators G05F1/573; disconnection after limiting H02H3/025)} · CPC title

  • comprising a parallel semiconductor switch being fired optically, e.g. using a photocoupler, · CPC title

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What does patent US10186857B2 cover?
Multiple relays are connected in parallel by including one or more semiconductor devices connected across the relay contacts. The semiconductor devices are triggered to conduct and shunt transient currents during the opening and closing of the relay contacts to protect the relay contacts from overcurrent and to eliminate arcing during relay switching. This permits a combination of smaller relay…
Who is the assignee on this patent?
Astronics Advanced Electronic Systems Corp
What technology area does this patent fall under?
Primary CPC classification H02H9/02. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 22 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).