Electronic device including a semiconductor memory

Patent metadata

Field	Value
Publication number	US-10186307-B2
Application number	US-201715823437-A
Country	US
Kind code	B2
Filing date	Nov 27, 2017
Priority date	Jul 4, 2014
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a MTJ (Magnetic Tunnel Junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure.

First claim

What is claimed is:

1. An electronic device comprising semiconductor memory, wherein the semiconductor memory includes:
a contact plug;
an electrode layer disposed over the contact plug and having a sidewall aligned with a sidewall of the contact plug;
a first stack structure disposed over the electrode layer and coupled to the electrode layer, wherein the first stack structure includes a MTJ (Magnetic Tunnel Junction) structure which includes a pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer; and
a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a pinning layer controlling a magnetization of the pinned layer,
wherein a width of the first stack structure is smaller than a width of the electrode layer and a width of the second stack structure,
wherein the first stack structure further includes a first capping layer which is nonmagnetic and conductive and covers a top surface of the MTJ structure, and a first hard mask layer which is conductive and positioned over the first capping layer.

2. The electronic device of claim 1 , wherein the electrode layer has a top surface which is planarized, and
wherein the entire first stack structure is on the top surface of the electrode layer.

3. The electronic device of claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the semiconductor memory is part of the cache memory unit in the processor.

4. The electronic device of claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and an outside,
wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

5. The electronic device of claim 1 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and from the storage device according to a command inputted from an outside;
a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and
an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

6. The electronic device of claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory is part of the memory unit in the microprocessor.

7. The electronic device of claim 1 , further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply;
a memory controller configured to control input and output of data to and from the memory according to a command inputted from an outside;
a buffer memory configured to buffer data exchanged between the memory and the outside; and
an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,
wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.

8. The electronic device of claim 1 , wherein the contact plug and the electrode layer are disposed in an interlayer dielectric layer.

9. The electronic device of claim 1 , wherein a width of the contact plug is smaller than the width of the first stack structure.

10. The electronic device of claim 1 , wherein the pinned magnetization direction of the pinned layer and the variable magnetization direction of the free layer are parallel to a stacking direction of the first stack structure.

11. The electronic device of claim 1 , further comprising a substrate formed under the contact plug and having a greater width than that of the contact plug.

12. The electronic device of claim 1 , wherein the pinning layer of the second stack structure has a magnetization direction same as that of the pinned magnetization direction of the first stack structure.

13. The electronic device of claim 1 , wherein the pinning layer of the second stack structure has a magnetization direction opposite to that of the pinned magnetization direction of the first stack structure.

14. An electronic device comprising semiconductor memory, wherein the semiconductor memory includes:
a contact plug;
an electrode layer disposed over the contact plug and having a sidewall aligned with a sidewall of the contact plug;
a first stack structure disposed over the electrode layer and coupled to the electrode layer, wherein the first stack structure includes a MTJ (Magnetic Tunnel Junction) structure which includes a pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer; and
a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a pinning layer controlling a magnetization of the pinned layer,
wherein a width of the first stack structure is smaller than a width of the electrode layer and a width of the second stack structure, and
wherein the second stack structure further includes a second capping layer which is nonmagnetic and conductive and covers a top surface of the pinning layer, and a second hard mask layer which is conductive and positioned over the second capping layer.

15. The electronic device of claim 14 , wherein the first stack structure further includes a first capping layer includes a material same as the second capping layer and covers a top surface of the MTJ structure, and a first hard

Assignees

• Sk Hynix Inc

Inventors

• Lee Min-Suk

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/02

  Electricity · mapped topic

• G06F2212/451

  Stack data · CPC title

• H01L43/08

  Electricity · mapped topic

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title