Driving circuit for array substrate, array substrate, display panel, and display device

Patent metadata

Field	Value
Publication number	US-10186228-B2
Application number	US-201615142015-A
Country	US
Kind code	B2
Filing date	Apr 29, 2016
Priority date	Aug 11, 2015
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

The present disclosure provides a driving circuit for an array substrate, an array substrate, a display panel, and a display device. The driving circuit comprises a plurality of driving signal lines, which are insulated from each other and are used for driving a display region of the array substrate; and at least one driving circuit protection line insulated from the plurality of driving signal lines, wherein a voltage of the driving circuit protection line is smaller than that of each of the plurality of driving signal lines.

First claim

What is claimed is:

1. A driving circuit for an array substrate, comprising:
a plurality of driving signal lines, which are insulated from each other and are used for driving a display region of the array substrate; and
at least one driving circuit protection line insulated from the plurality of driving signal lines,
wherein a voltage applied to the driving circuit protection line is smaller than a voltage applied to the plurality of driving signal lines;
the driving signal line comprises a first metal layer, a second metal layer and a third metal layer which connects the first metal layer with the second metal layer, and
each driving signal is applied to a corresponding electrode in the display region via the third metal layer.

2. The driving circuit of claim 1 , wherein an end of the first metal layer and an end of the second metal layer, which face each other, are provided therein with contact holes respectively, and the third metal layer is connected with the second metal layer and the first metal layer through the contact holes respectively.

3. The driving circuit of claim 1 , wherein a negative voltage signal is applied to the driving circuit protection line.

4. The driving circuit of claim 3 , wherein a negative voltage signal whose absolute value is smaller than the absolute value of the negative voltage signal applied to the driving circuit protection line is applied to each of the plurality of driving signal lines.

5. The driving circuit of claim 3 , wherein a positive voltage signal is applied to each of the plurality of driving signal lines.

6. The driving circuit of claim 3 , wherein a direct current negative voltage signal is applied to the driving circuit protection line.

7. The driving circuit of claim 1 , wherein the third metal layer comprises transparent electrode material.

8. The driving circuit of claim 1 , wherein the first metal layer and a gate are provided in the same layer.

9. The driving circuit of claim 1 , wherein the second metal layer, a source and a drain are provided in the same layer.

10. The driving circuit of claim 1 , wherein the third metal layer and a pixel electrode are provided in the same layer.

11. An array substrate, comprising the driving circuit of claim 1 .

12. A display panel, comprising the array substrate of claim 11 .

13. A display device, comprising the display panel of claim 12 .

14. A driving circuit for an array substrate, comprising:
a plurality of driving signal lines, which are insulated from each other and are used for driving a display region of the array substrate, and
at least one driving circuit protection line insulated from the plurality of driving signal lines,
wherein a voltage applied to the driving circuit protection line is smaller than a voltage applied to the plurality of driving signal lines,
wherein the driving circuit protection line comprises a first metal layer, a second metal layer and a third metal layer which connects the first metal layer with the second metal layer.

15. The driving circuit of claim 14 , wherein an end of the first metal layer and an end of the second metal layer, which face each other, are provided therein with contact holes respectively, and the third metal layer is connected with the second metal layer and the first metal layer through the contact holes respectively.

16. The driving circuit of claim 14 , wherein the third metal layer comprises transparent electrode material.

17. The driving circuit of claim 14 , wherein the first metal layer and a gate are provided in the same layer.

18. The driving circuit of claim 14 , wherein the second metal layer, a source and a drain are provided in the same layer.

19. The driving circuit of claim 14 , wherein the third metal layer and a pixel electrode are provided in the same layer.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co
• Beijing Boe Display Tech Co

Inventors

• Hao Yuanyuan
• Hao Zhaohui
• Yao Zhixiao

Classifications

• G09G2320/04

  Maintaining the quality of display appearance · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G09G3/3614

  Control of polarity reversal in general · CPC title

• G09G2300/0421

  Structural details of the set of electrodes · CPC title

• G09G3/3696 Primary

  Generation of voltages supplied to electrode drivers · CPC title