Method for switching address spaces via an intermediate address space

Patent metadata

Field	Value
Publication number	US-10185664-B1
Application number	US-201715639800-A
Country	US
Kind code	B1
Filing date	Jun 30, 2017
Priority date	Jun 30, 2017
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A method of re-mapping a boot loader image from a first to a second address space includes: determining a difference in a virtual address of the boot loader image in the first and second address spaces; building page tables for a third address space that maps a code section within the boot loader image at first and second address ranges separated by the difference and the code section causes execution to jump from a first instruction in the first address range to a second instruction in the second address range; executing an instruction of the code section in the first address space using pages tables for the first address space; executing the first instruction and then the second instruction using the page tables for the third address space; and executing an instruction of the boot loader image in the second address space using page tables for the second address space.

First claim

What is claimed is:

1. A method of re-mapping a boot loader image from a first address space to a target location in a second address space, wherein first pages tables map the first address space to a machine address space and second page tables map the second address space to the machine address space, comprising:
(a) determining a difference in a virtual address of the boot loader image in the first address space and a corresponding virtual address of the boot loader image in the second address space;
(b) building page tables for a third address space that maps a code section within the boot loader image at a first address range and a second address range, wherein the two address ranges are separated by the determined difference and the code section when executed causes execution to jump from a first instruction that is mapped in the first address range to a second instruction that is mapped in the second address range;
(c) executing, in a processor, an instruction in the code section that is mapped in the first address space using pages tables for the first address space;
(d) executing, in the processor, the first instruction and then the second instruction using the page tables for the third address space; and
(e) executing, in the processor, an instruction in the boot loader image that is mapped in the second address space using page tables for the second address space.

2. The method of claim 1 , further comprising:
switching page tables used by a memory management unit of the processor from the pages tables for the first address space to the pages tables for the third address space between (c) and (d); and
switching page tables used by the memory management unit of the processor from the pages tables for the third address space to the pages tables for the second address space between (d) and (e).

3. The method of claim 2 , wherein a page table root includes a pointer that points to the page tables used by the memory management unit and the page tables are switched by changing the pointer of the page table root.

4. The method of claim 2 , further comprising:
after switching the page tables, initializing the memory management unit and flushing a translation lookaside buffer of the memory management unit.

5. The method of claim 1 , wherein the virtual address of the boot loader image in the first address space is a starting address of the boot loader image in the first address space and the corresponding virtual address of the boot loader image in the second address space is a starting address of the target location in the second address space to which the boot loader image is being re-mapped.

6. The method of claim 5 , wherein the difference in the virtual address of the boot loader image in the first address space and the corresponding virtual address of the boot loader image in the second address space is determined by:
determining a first offset between the starting address of the boot loader image in the first address space and a machine address to which the starting address of the boot loader image in the first address space is mapped;
determining a second offset between the starting address of the target location in the second address space to which the boot loader image is being re-mapped and the machine address; and
determining the difference as a difference between the first offset and the second offset.

7. A non-transitory computer readable medium comprising instructions for causing a processor to perform a method of re-mapping a boot loader image from a first address space to a target location in a second address space, wherein first pages tables map the first address space to a machine address space and second page tables map the second address space to the machine address space, and the method comprises:
(a) determining a difference in a virtual address of the boot loader image in the first address space and a corresponding virtual address of the boot loader image in the second address space;
(b) building page tables for a third address space that maps a code section within the boot loader image at a first address range and a second address range, wherein the two address ranges are separated by the determined difference and the code section when executed causes execution to jump from a first instruction that is mapped in the first address range to a second instruction that is mapped in the second address range;
(c) executing an instruction in the code section that is mapped in the first address space using pages tables for the first address space;
(d) executing the first instruction and then the second instruction using the page tables for the third address space; and
(e) executing an instruction in the boot loader image that is mapped in the second address space using page tables for the second address space.

8. The non-transitory computer readable medium of claim 7 , wherein the method further comprises:
switching page tables used by a memory management unit of the processor from the pages tables for the first address space to the pages tables for the third address space between (c) and (d); and
switching page tables used by the memory management unit of the processor from the pages tables for the third address space to the pages tables for the second address space between (d) and (e).

9. The non-transitory computer readable medium of claim 8 , wherein a page table root includes a pointer that points to the page tables used by the memory management unit and the page tables are switched by changing the pointer of the page table root.

10. The non-transitory computer readable medium of claim 8 , wherein the method further comprises:
after switching the page tables, initializing the memory management unit and flushing a translation lookaside buffer of the memory management unit.

11. The non-transitory computer readable medium of claim 7 , wherein the virtual address of the boot loader image in the first address space is a starting address of the boot loader image in the first address space and the corresponding virtual address of the boot loader image in the second address space is a starting address of the target location in the second address space to which the boot loader image is being re-mapped.

12. The non-transitory computer readable medium of claim 11 , wherein the difference in the virtual address of the boot loader image in the first address space and the corresponding virtual address of the boot loader image in the second address space is determined by:
determining a first offset between the starting address of the boot loader image in the first address space and a machine address to which the starting address of the boot loader image in the first address space is mapped;
determining a second offset between the starting address of the target location in the second address space to which the boot loader image is being re-mapped and the machine address; and
determining the difference as a difference between the first offset and the second offset.

13. A computer system, comprising:
a system memory in which a boot loader image, first pages tables that map a first address space to a machine address space of the system memory, and second page tables map a second address space to the machine address space of the system memory, are stored; and
a processor including a memory management unit and a translation lookaside buffer, the processor being configured to re-map the boot loader image from the first address space to a target location in the second address space by carrying out the steps of:
(a) determining a difference in a virtual address of the boot loader image in the first address space and a corresponding vir

Assignees

• Vmware Inc

Inventors

• Warkentin Andrei
• Laplace Cyprien
• Duchesne Regis
• Fainkichen Alexander
• Li Ye

Classifications

• G06F2212/651

  Multi-level translation tables · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/682

  Multiprocessor TLB consistency · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F9/4401 Primary

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title