Scalable autonomic message-transport with synchronization

Patent metadata

Field	Value
Publication number	US-10185606-B2
Application number	US-201615096966-A
Country	US
Kind code	B2
Filing date	Apr 12, 2016
Priority date	Apr 12, 2016
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

First claim

What is claimed is:

1. A method, comprising:
receiving, by a first autonomic transport system (ATS) block of a first cluster in a circuit, a first request from a first computation element (CE) for transferring a first message stored in a first memory of the first cluster to a second memory, the first ATS block, the first memory and the first CE being a part of the first cluster, wherein the first ATS block is separate and distinct from the first CE and is configured to perform inter-process communication (IPC) for the first CE and to manage message transfer within the first cluster and between the first cluster and another cluster, the second memory belonging to the first cluster, the first request specifying a location of the first message in the first memory;
placing, prior to transmitting the first message, a first message descriptor in an ingress queue (iQ) of the first cluster, the first message descriptor indicating a location of the first message in the first memory;
transferring, by the first ATS block in response to receipt of the first request, the first message to the second memory;
receiving, by the first ATS block of the first cluster in the circuit, a second request from a second CE for transferring a second message stored in a third memory of the first cluster to a fourth memory, the third memory and the second CE also being a part of the first cluster, wherein the first ATS block is separate and distinct from the second CE and is configured to perform IPC for the second CE, the fourth memory belonging to a second cluster different than the first cluster, the second request specifying a location of the second message in the third memory;
placing, prior to transmitting the second message, a second message descriptor in the iQ of the first cluster, the second message descriptor indicating a location of the second message in the third memory; and
transferring, by the first ATS block in response to the receipt of the second request, the second message to a second ATS block in the second cluster without using a direct memory access technique.

2. The method of claim 1 , wherein the first ATS block comprises an interposer (ITP) configured to transfer messages to an ITP of the second cluster, a buffer manager (BM) configured to manage buffers for the messages, a queue manager (QM) configured to manage queues of the messages, and a task scheduler (TS) configured to schedule a ready task for the first CE and the second CE.

3. The method of claim 1 , further comprising:
freeing, by the first ATS block, a buffer storing the first message in the first memory after transferring the first message.

4. The method of claim 1 , further comprising:
placing the first message in the iQ of the first cluster before the first message is transmitted.

5. The method of claim 1 , wherein the circuit is a system-on-chip or the circuit comprises multiple system-on-chips.

6. The method of claim 1 , further comprising:
reading, by the first ATS block, the first message stored in the first memory of the first cluster in the circuit.

7. The method of claim 1 , wherein the second cluster comprises a third CE, a fifth memory, and a second ATS block, the second ATS block being configured to receive the second message.

8. The method of claim 1 , wherein the first memory and the third memory are the same memory.

9. The method of claim 1 , wherein the first CE and the second CE are the same CE.

10. The method of claim 1 , further comprising:
receiving, by the first ATS block of the first cluster in the circuit, a third request from a third CE for transferring a third message stored in a fifth memory of the first cluster to a sixth memory, the first ATS block, the fifth memory and the third CE being a part of the first cluster, wherein the first ATS block is separate and distinct from the third CE and is configured to perform IPC for the third CE and to manage message transfer within the first cluster and between the first cluster and another cluster, the fifth memory belonging to the first cluster;
placing, prior to transmitting the third message, a second message descriptor in the iQ of the first cluster, the second message descriptor indicating a location of the third message in the fifth memory;
transferring, by the first ATS block in response to receipt of the first request and without copying the third message from the fifth to the sixth memory, the second message descriptor indicating the location of the third message to an egress queue (eQ) of the first cluster.

11. A method, comprising:
allocating, by an autonomic transport system (ATS) block of a first cluster in a circuit, a buffer in a memory of the first cluster for receiving a message by the ATS block from a second cluster different than the first cluster, the ATS block and the memory being a part of the first cluster, wherein the first cluster comprises a computation element (CE) separate and different from the ATS block, and wherein the ATS block is configured to perform inter-process communication (IPC) for the CE and to manage message transfer within the first cluster and between the first cluster and another cluster;
receiving, by the ATS block of the first cluster in the circuit, the message from the second cluster different than the first cluster;
writing, by the ATS block, the message received by the ATS block from the second cluster into the buffer without using a direct memory access technique, the message being one of a plurality of messages required for the CE to execute a task;
monitoring, by the ATS block, whether the plurality of messages have been received without interrupting the CE; and
scheduling, by the ATS block based at least in part on receipt of the plurality of messages, the task for the CE.

12. The method of claim 11 , wherein the second cluster is in the circuit, the second cluster communicating with the first cluster.

13. The method of claim 11 , further comprising sending a grant to the second cluster, the grant allowing transmission of the message.

14. The method of claim 11 , wherein the second cluster comprises a second CE, a second memory, and a second ATS block configured to perform inter-process communication (IPC) for the second CE, and wherein the message is transmitted by the second ATS block of the second cluster.

15. The method of claim 14 , wherein the message is transmitted by the second ATS block to the first cluster upon a request from the second CE.

16. The method of claim 11 , further comprising placing a message descriptor in an egress queue of the first cluster after writing the message, the message descriptor indicating a location of the buffer in the memory.

17. The method of claim 11 , further comprising managing, by the ATS block, synchronization of the message.

18. The method of claim 11 , wherein the ATS block comprises an interposer (ITP) configured to transmit and receive messages, a buffer manager (BM) configured to manage buffers for the messages, and a queue manager (QM) configured to manage queues of the messages.

19. The method of claim 18 , further comprising:
sending, by the QM, a synchronization signal to a task scheduler (TS) of the ATS block, the synchronization signal indicating readiness of a task associated with the message, wherein the task scheduler is configured to schedule tasks to run in the first cluster.

20. The method of claim 11 , wherein the circuit is a system-on-chip or comprises multiple system-on-chips.

21. The method of claim 11 , wherein the plurality of messag

Assignees

• Futurewei Technologies Inc

Inventors

• Yan Peter
• Gatherer Alan
• Chandra Alex Elisa
• McFearin Lee Dobson
• Brown Mark
• Bhattacharya Debashis
• Yu Fang
• Chen Xingfeng
• Bei Yan
• Ning Ke
• Huang Chushun
• Sun Tong
• Chen Xiaotao

Classifications

• G06F9/546 Primary

  Message passing systems or structures, e.g. queues · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title