Write buffer design for high-latency memories

Patent metadata

Field	Value
Publication number	US-10185498-B2
Application number	US-201615184996-A
Country	US
Kind code	B2
Filing date	Jun 16, 2016
Priority date	Jun 16, 2016
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A memory system includes a write buffer, a main memory having a higher latency than the write buffer, and a memory controller. In response to a write request indicating first data for storing at a write address in the main memory, the memory controller adds a new write entry in the write buffer, where the new write entry includes the write address and the first data, and updates a pointer of a previous write entry in the write buffer to point to the new write entry. In response to a write-back instruction, the memory controller traverses a plurality of write entries stored in the write buffer, and writes into the main memory second data of the previous write entry and the first data of the new write entry.

First claim

What is claimed is:

1. A memory system, comprising:
a write buffer;
a main memory having a higher latency than the write buffer;
a memory controller coupled with the main memory and with the write buffer, wherein the memory controller is configured to:
create a chronological linked list of write entries by:
in response to a write request indicating first data for storing at a write address in the main memory, adding a new write entry in the write buffer, wherein the new write entry includes the write address and the first data, and
in response to the write request, updating a pointer of a previous write entry in the write buffer to point to the new write entry;

issue a write-back instruction in response to detecting at least a threshold amount of available bandwidth for the main memory; and

in response to the write-back instruction, traverse a plurality of write entries stored in the write buffer including the previous write entry and the new write entry, and write into the main memory second data of the previous write entry and the first data of the new write entry.

2. The memory system of claim 1 , wherein:
the write buffer comprises dynamic random access memory (DRAM), and
the main memory comprises non-volatile memory (NVM).

3. The memory system of claim 1 , wherein:
for each write entry of the plurality of write entries, the write entry includes an address field, a data field, a valid bit, a dirty bit, a hash pointer, and a next write pointer that points to another write entry of the plurality of write entries that is newer than the write entry, and
the pointer of the previous write entry is the next write pointer of the previous write entry.

4. The memory system of claim 1 , wherein the memory controller is further configured to, after adding the new write entry, add a subsequent new write entry in response to a subsequent write request prior to closing a memory row opened for the new write entry.

5. The memory system of claim 1 , wherein the memory controller is further configured to traverse the new write entry and the previous write entry by following the pointer of the previous write entry to the new write entry.

6. The memory system of claim 5 , wherein the memory controller is further configured to invalidate each of the previous write entry and the new write entry in response to the write-back instruction.

7. The memory system of claim 1 , further comprising a Bloom filter, wherein the memory controller is further configured to:
in response to the write request, add the write address to the Bloom filter; and
in response to a read request indicating a read address, determine whether the Bloom filter returns a match for the read address.

8. The memory system of claim 7 , wherein the memory controller is further configured to, if the Bloom filter returns a match for the read address, contemporaneously issue the read request to the write buffer and to the main memory.

9. A method, comprising:
creating a chronological linked list of write entries by, in response to a write request indicating first data for storing at a write address in a main memory,
adding a new write entry in a write buffer, wherein the new write entry includes the write address and the first data, and
updating a pointer of a previous write entry in the write buffer to point to the new write entry;

issuing a write-back instruction in response to detecting at least a threshold amount of available bandwidth for the main memory; and
in response to the write-back instruction,
traversing a plurality of write entries stored in the write buffer including the previous write entry and the new write entry, and
writing into the main memory second data of the previous write entry and the first data of the new write entry, wherein the main memory has a higher latency than the write buffer.

10. The method of claim 9 , further comprising, after adding the new write entry, adding a subsequent new write entry in response to a subsequent write request prior to closing a memory row opened for the new write entry.

11. The method of claim 9 , wherein traversing the new write entry and the previous write entry further comprises following the pointer of the previous write entry to the new write entry.

12. The method of claim 11 , further comprising invalidating each of the previous write entry and the new write entry in response to the write-back instruction.

13. The method of claim 9 , further comprising:
in response to the write request, adding the write address to a Bloom filter; and
in response to a read request indicating a read address, determining whether the Bloom filter returns a match for the read address.

14. The method of claim 13 , further comprising, if the Bloom filter returns a match for the read address, contemporaneously issuing the read request to the write buffer and to the main memory.

15. A system, comprising:
a write buffer;
a main memory having a higher latency than the write buffer;
a host processor comprising a memory controller, wherein the memory controller is coupled with the main memory and with the write buffer, and wherein the memory controller is configured to:
create a chronological linked list of write entries by, for each write request of a plurality of write requests issued by the host processor, wherein the write request indicates first data for storing at a write address in the main memory,
adding a new write entry to a plurality of write entries in the write buffer, wherein the new write entry includes the write address and the first data, and
updating a next write pointer of a previous write entry in the write buffer to point to the new write entry, and

in response to a write-back instruction issued by the host processor, traverse the plurality of write entries in chronological order by, for each write entry of the plurality of write entries, copying data of the write entry to the main memory, wherein the host processor is configured to issue the write-back instruction in response to detecting at least a threshold amount of available bandwidth for the main memory.

16. The system of claim 15 , wherein the memory controller is further configured to traverse the plurality of write entries by, for each write entry of the plurality of write entries, following the pointer of the write entry to a next write entry of the plurality of write entries, and invalidating the write entry.

17. The system of claim 15 , wherein:
the write buffer comprises dynamic random access memory (DRAM), and
the main memory comprises non-volatile memory (NVM).

18. The system of claim 15 , further comprising a Bloom filter, wherein the memory controller is further configured to:
in response to the write request, add the write address to the Bloom filter; and
in response to a read request indicating a read address, determine whether the Bloom filter returns a match for the read address, and
if the Bloom filter returns a match for the read address, contemporaneously issue the read request to the write buffer and to the main memory.

Assignees

• Advanced Micro Devices Inc

Inventors

• Roberts David A

Classifications

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0616

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/068

  Hybrid storage device · CPC title