Apparatus and method for extending frequency range of a circuit and for over-clocking or under-clocking

Patent metadata

Field	Value
Publication number	US-10185349-B2
Application number	US-201314917928-A
Country	US
Kind code	B2
Filing date	Dec 3, 2013
Priority date	Dec 3, 2013
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.

First claim

We claim:

1. An apparatus comprising:
a locked loop having a feedback divider, wherein the locked loop is to receive a reference clock and to compare the reference clock with a feedback clock, wherein the feedback clock is output from the feedback divider, and wherein the locked loop is to generate an output clock;
a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and
a control logic to dynamically adjust first and second divider ratios for the feedback divider and the post locked loop divider, respectively, to over-clock or under-clock the base clock such that the locked loop remains locked while being over-clocked or under-clocked.

2. The apparatus of claim 1 , wherein the locked loop is one of a phase locked loop (PLL) or frequency locked loop (FLL).

3. The apparatus of claim 2 further comprises one or more registers to store code for controlling the oscillator when the PLL is locked.

4. The apparatus of claim 3 , wherein the control logic is accessible by software or hardware.

5. The apparatus of claim 4 , wherein the feedback divider is a fractional divider, and wherein the control unit is operable to adjust the first divider ratio to increase frequency of the output clock while the control logic is to maintain lock for the PLL.

6. The apparatus of claim 5 , wherein the control logic is operable to maintain the second divider ratio for the post PLL divider while the control logic is to maintain the first divider ratio.

7. The apparatus of claim 6 , wherein the control logic is to track the code and is to update the first and second divider ratios.

8. The apparatus of claim 7 , wherein the control logic is to reapply the stored code for the PLL and is to provide a synchronized update for the first and second divider ratios to the feedback divider and the post PLL divider, respectively.

9. The apparatus of claim 8 , wherein the control unit is to extend frequency range of the base clock.

10. The apparatus of claim 9 , wherein the PLL further comprises a time-to-digital (TDC) unit to receive the reference clock and the feedback clock.

11. The apparatus of claim 10 , wherein the PLL further comprises a loop filter to filter output of the TDC.

12. The apparatus of claim 11 , wherein the PLL further comprises an oscillator which is operable to oscillate according to an output of the loop filter, wherein the oscillator is to generate the output clock.

13. The apparatus of claim 12 , wherein the oscillator is a digitally controlled oscillator (DCO).

14. The apparatus of claim 12 , wherein the output clock of the oscillator is received by the feedback divider to generate the feedback clock.

15. A method comprising:
locking a phase locked loop (PLL) to provide a base clock;
storing a snapshot of codes or values associated with one or more components of the PLL when the PLL is locked;
updating a first divider ratio of a feedback divider of the PLL while maintaining the PLL in locked state; and
dynamically updating a second divider ratio of a post PLL divider while maintaining the first divider ratio.

16. The method of claim 15 further comprises:
determining whether the base clock is operating at a predetermined top frequency.

17. The method of claim 16 further comprises determining when a feedback clock and the base clock are synchronized.

18. The method of claim 17 further comprises updating the first and second ratios when the feedback clock and the base clock are synchronized.

19. A system comprising:
a memory unit;
a processor coupled to the memory unit, the processor operable to be over-clocked or under-clocked, the processor having an apparatus which comprises:
a locked loop having a feedback divider, wherein the locked loop is to receive a reference clock and to compare the reference clock with a feedback clock, wherein the feedback clock is output from the feedback divider, and wherein the locked loop is to generate an output clock;
a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and
a control logic to dynamically adjust first and second divider ratios for the feedback divider and the post locked loop divider, respectively, to over-clock or under-clock the base clock such that the locked loop remains locked while being over-clocked or under-clocked; and

a wireless interface to allow the processor to communicate with another device.

20. The system of claim 19 further comprises a display unit.

Assignees

• Intel Corp

Inventors

• Musunuri Surya
• Rapeta Jagannadha R
• Elzinga Mark L
• Park Young Min
• Fulton Robert

Classifications

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F13/36

  for access to common bus or bus system · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/183

  a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number {(H03L7/1806 takes precedence)} · CPC title

• G06F13/4068

  Electrical coupling · CPC title