Stacked power supply for reduced current consumption

Patent metadata

Field	Value
Publication number	US-10185347-B2
Application number	US-201514799638-A
Country	US
Kind code	B2
Filing date	Jul 15, 2015
Priority date	Dec 18, 2014
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A circuit arrangement comprising a first capacitor and a second capacitor which are arranged in series between a high potential and a low potential is described. The circuit arrangement comprises first power consuming circuitry which is arranged in parallel to the first capacitor. The first power consuming circuitry ( 113 ) consumes electrical power at a first voltage. The circuit arrangement comprises second power consuming circuitry which is arranged in parallel to the second capacitor. The second power consuming circuitry consumes electrical power at a second voltage, wherein a magnitude of the sum of the first voltage and the second voltage is smaller than an absolute difference between the high potential and the low potential. The circuit arrangement sets a voltage at the first capacitor in accordance to the first voltage and to set a voltage at the second capacitor in accordance to the second voltage.

First claim

What is claimed is:

1. A circuit arrangement comprising,
a first capacitor and a second capacitor which are arranged in series between a high potential and a low potential;
first power consuming circuitry which is arranged in parallel to the first capacitor; wherein the first power consuming circuitry consumes electrical power at a first voltage;
second power consuming circuitry which is arranged in parallel to the second capacitor; wherein the second power consuming circuitry consumes electrical power at a second voltage; wherein a magnitude of the sum of the first voltage and the second voltage is smaller than an absolute difference between the high potential and the low potential; and
voltage setting means which are configured to set a voltage at the first capacitor in accordance to the first voltage and to set a voltage at the second capacitor in accordance to the second voltage wherein the voltage setting means comprise
a first voltage source and a second voltage source which are arranged in series; wherein the first voltage source is configured to provide electrical power at the first voltage; wherein the second voltage source is configured to provide electrical power at the second voltage;
a first current mirror which is coupled to a high side port of the first voltage source and which is coupled to a high side port of the first power consuming circuitry; and
a second current mirror which is coupled to a high side port of the second voltage source and which is coupled to a high side port of the second power consuming circuitry.

2. The circuit arrangement of claim 1 , wherein the voltage setting means comprise a shunt regulator, which is configured to set the voltage at the second capacitor to the second voltage.

3. The circuit arrangement of claim 1 , further comprising circuitry which is configured to provide a bi-directional level shift between a first reference level of the first power consuming circuitry and a second reference level of the second power consuming circuitry.

4. The circuit arrangement of claim 1 , wherein
the first power consuming circuitry comprises one or more electronic components which are each operated at the first voltage; and
the second power consuming circuitry comprises one or more electronic components which are each operated at the second voltage.

5. The circuit arrangement of claim 1 , wherein
the first power consuming circuitry comprises one or more digital components; and
the second power consuming circuitry comprises one or more analog components.

6. The circuit arrangement of claim 1 , wherein the circuit arrangement comprises a driver circuit for a light emitting diode.

7. A method for providing electrical energy to first power consuming circuitry and to second power consuming circuitry; wherein the first power consuming circuitry consumes electrical power at a first voltage; and wherein the second power consuming circuitry consumes electrical power at a second voltage; the method comprising the steps of:
arranging a first capacitor and a second capacitor in series between a high potential and a low potential; wherein a magnitude of the sum of the first voltage and the second voltage is smaller than an absolute difference between the high potential and the low potential;
arranging the first power consuming circuitry in parallel to the first capacitor;
arranging the second power consuming circuitry in parallel to the second capacitor;
setting a voltage at the first capacitor in accordance to the first voltage; and
setting a voltage at the second capacitor in accordance to the second voltage
providing a first voltage source and a second voltage source which are arranged in series; wherein the first voltage source provides electrical power at the first voltage; wherein the second voltage source provides electrical power at the second voltage;
providing a first current mirror which is coupled to a high side port of the first voltage source and which is coupled to a high side port of the first power consuming circuitry; and
providing a second current mirror which is coupled to a high side port of the second voltage source and which is coupled to a high side port of the second power consuming circuitry.

8. The method of claim 7 , further comprising the step of:
setting the voltage at the second capacitor to the second voltage by a shunt regulator.

9. The method of claim 7 , further comprising the step of:
providing circuitry to provide a bi-directional level shift between a first reference level of the first power consuming circuitry and a second reference level of the second power consuming circuitry.

10. The method of claim 7 , wherein
the first power consuming circuitry comprises one or more electronic components which are each operated at the first voltage; and
the second power consuming circuitry comprises one or more electronic components which are each operated at the second voltage.

11. The method of claim 7 , wherein
the first power consuming circuitry comprises one or more digital components; and
the second power consuming circuitry comprises one or more analog components.

12. The method of claim 7 , wherein the circuit arrangement comprises a driver circuit for a light emitting diode.

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Knoedgen Horst

Classifications

• G05F3/16

  being semiconductor devices · CPC title

• G05F3/26 Primary

  Current mirrors · CPC title

• G05F1/577

  for plural loads · CPC title

• G05F3/18

  using Zener diodes · CPC title