Downstream device service latency reporting for power management
US-2015257101-A1 · Sep 10, 2015 · US
Downstream device service latency reporting for power management
US10182398B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10182398-B2 |
| Application number | US-201715453208-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 8, 2017 |
| Priority date | Dec 31, 2008 |
| Publication date | Jan 15, 2019 |
| Grant date | Jan 15, 2019 |
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- Title
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Abstract
Official abstract text for this publication.
An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.
First claim
Opening claim text (preview).
What is claimed is: 1. A system comprising: a processor; a memory controller coupled to the processor to provide access to a system memory; and an interface controller to communicate with an endpoint device, the interface controller coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device; wherein the endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state; and wherein the service latency tolerance value for the first state is greater than the service latency tolerance value for the second state. 2. The system of claim 1 , wherein the endpoint device is a peripheral component interconnect express (PCIe) endpoint device. 3. The system of claim 1 , further comprising a communication interface to communicate over a network. 4. The system of claim 1 , further comprising a graphics controller.
Assignees
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Classifications
Cross-Sectional Technologies · mapped topic
Cross-Sectional Technologies · mapped topic
One way delays · CPC title
comprising thermal management · CPC title
Cross-Sectional Technologies · mapped topic
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Frequently asked questions
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- What does patent US10182398B2 cover?
- An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to stor…
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H04W52/0225. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 15 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).