Ethernet-based communication system

US10181920B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10181920-B2
Application numberUS-201415321997-A
CountryUS
Kind codeB2
Filing dateJun 27, 2014
Priority dateJun 27, 2014
Publication dateJan 15, 2019
Grant dateJan 15, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An ethernet-based communication system is provided. The communication system comprises: a first unit configured to generate a reference clock signal by using an input first ethernet signal, multiplex the first ethernet signal and a second ethernet signal in response to the reference clock signal, and output the multiplexed ethernet signals; a second unit configured to generate the reference clock signal by using the multiplexed ethernet signals, separate the second ethernet signal from the multiplexed ethernet signals in response to the reference clock signal, and output the first ethernet signal; and a transmission medium for connecting the first and second units and transmitting the multiplexed ethernet signals from the first unit to the second unit.

First claim

Opening claim text (preview).

The invention claimed is: 1. A communication system comprising: a transmitting device comprising at least one processor configured to generate a reference clock signal by using a first ethernet signal which is input to the transmitting device and has a first transmission rate, multiplex the first ethernet signal and a second ethernet signal having a second transmission rate which is different from the first transmission rate in response to the reference clock signal, and output the multiplexed ethernet signal; a receiving device comprising at least one processor configured to generate the reference clock signal by using the multiplexed ethernet signal, separate the second ethernet signal from the multiplexed ethernet signal in response to the reference clock signal, and output the first ethernet signal; and a transmission cable for connecting the transmitting device and the receiving device and transmitting the multiplexed ethernet signal from the transmitting device to the receiving device, wherein a transmission rate of the multiplexed ethernet signal is substantially equal to the first transmission rate. 2. The communication system of claim 1 , wherein the first transmission rate is a transmission rate in gigabits per second, and the second transmission rate is a transmission rate in megabits per second. 3. The communication system of claim 1 , wherein the transmitting device comprises: a first restorer configured to restore a clock signal using the first ethernet signal; a first serializer/deserializer configured to parallelize the first ethernet signal with first internal signals having the second transmission rate and output a result; a first phase lock loop configured to generate a reference clock signal by using the restored clock signal; a first coding part configured to perform coding process on the first internal signals and output the first internal signals in response to the reference clock signal; and a second serializer/deserializer configured to serialize the first internal signals, which have been coding processed in response to the reference clock signal, and the second ethernet signal to have the first transmission rate, and configured to output the multiplexed ethernet signal. 4. The communication system of claim 3 , wherein the first coding part comprises: a first decoder configured to decode the first internal signals by 10B8B and output the decoded first internal signals; and a first encoder configured to encode the 10B8B decoded first internal signals by 8B9B and output a result. 5. The communication system of claim 1 , wherein the receiving device comprises: a second restorer configured to restore a clock signal using the multiplexed ethernet signal; a third serializer/deserializer configured to parallelize the multiplexed ethernet signal with second internal signals having the second transmission rate and output a result; a second phase lock loop configured to generate a reference clock signal by using the restored clock signal; a divider configured to separate the second ethernet signal from the second internal signals in response to the reference clock signal and output third internal signals; a second coding part configured to perform coding process on the third internal signals and output the third internal signals in response to the reference clock signal; and a fourth serializer/deserializer configured to serialize the coding processed third internal signals in response to the reference clock signal, to have the first transmission rate, and configured to output the first ethernet signal. 6. The communication system of claim 5 , wherein the second coding part comprises: a second decoder configured to decode the third internal signals by 9B8B; and a second encoder configured to encode the 9B8B decoded third internal signals by 8B10B. 7. The communication system of claim 1 , wherein the first transmission rate is 1.25 Gbps, and the second transmission rate is 125 Mbps. 8. The communication system of claim 1 , wherein the transmission cable is an optical transmission cable.

Assignees

Inventors

Classifications

  • Repeaters · CPC title

  • H04J3/0641Primary

    Change of the master or reference, e.g. take-over or failure of the master · CPC title

  • Time-division multiplex systems · CPC title

  • with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

  • using special codes as synchronising signal · CPC title

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What does patent US10181920B2 cover?
An ethernet-based communication system is provided. The communication system comprises: a first unit configured to generate a reference clock signal by using an input first ethernet signal, multiplex the first ethernet signal and a second ethernet signal in response to the reference clock signal, and output the multiplexed ethernet signals; a second unit configured to generate the reference clo…
Who is the assignee on this patent?
Solid Systems Inc, Solid Inc
What technology area does this patent fall under?
Primary CPC classification H04J3/0641. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 15 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).